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    • 8. 发明授权
    • Jack
    • 插口
    • US06869315B2
    • 2005-03-22
    • US10471359
    • 2003-04-14
    • Yuji NakaiKoji Matsumoto
    • Yuji NakaiKoji Matsumoto
    • H01R24/04
    • H01R24/58H01R12/57H01R24/40H01R2103/00H01R2107/00
    • In order to configure a jack (J) that realizes a favorable conductive state by bringing a tip electrode (10) at a front end of a plug (P) into reliable contact with a contact without making the jack bigger, a contact unit (CU) having a pair of tip contacts (CT) that contact the tip electrode (10) at the front end of the plug (P) in an embracing fashion is incorporated in a body (20). The contact unit (CU) is made of a linking portion (23), intermediate portions (24) that extend from both ends of the linking portion (23) towards an aperture side of the plug insertion hole (H), and folded portions (25) that are folded over from the ends of the intermediate portions (24) to the inner end side of the plug insertion hole (H), projecting into the plug insertion hole (H), the contact unit being formed in one piece by bending a band-shaped conductor, such as a copper alloy, and the tip contacts (CT) being formed on a free end side of the folded portions (25).
    • 为了构成通过将插头(P)的前端的前端电极(10)与接点可靠地接触而不使插座变大而实现良好的导通状态的插座(J),接触单元(CU )具有一对尖端触点(CT),其以包围的方式接触插塞(P)的前端处的尖端电极(10)并入主体(20)中。 接触单元(CU)由连接部分(23),从连接部分(23)的两端延伸到插头插入孔(H)的孔侧的中间部分(24)和折叠部分 25),其从中间部分(24)的端部折叠到插头插入孔(H)的内端侧,突出到插头插入孔(H)中,接触单元通过弯曲形成为一体 诸如铜合金的带状导体,并且尖端触头(CT)形成在折叠部分(25)的自由端侧上。
    • 9. 发明授权
    • Fast fourier transforming apparatus and method, variable bit reverse circuit, inverse fast fourier transforming apparatus and method, and OFDM receiver and transmitter
    • 快速傅里叶变换装置和方法,可变位反向电路,反向快速傅里叶变换装置和方法,以及OFDM接收机和发射机
    • US06247034B1
    • 2001-06-12
    • US09371923
    • 1999-08-11
    • Yuji NakaiAkihiro Furuta
    • Yuji NakaiAkihiro Furuta
    • G06F1714
    • G06F17/141
    • In fast Fourier transform, a necessary memory capacity is decreased, thereby decreasing a cost. The fast Fourier transform is performed on a symbol stored in a RAM by a butterfly operation unit in accordance with a RAM address generated by a RAM address generator. A RAM address conversion unit converts an input/output dummy address into an input/output real address by conducting bit reverse by a frequency specified in accordance with an input/output bit reverse signal, and converts a butterfly operation dummy address into a butterfly operation real address by conducting the bit reverse by a frequency specified in accordance with a butterfly operation bit reverse signal. In this manner, among output data of one symbol and input data of another symbol to be stored in the RAM subsequently to the output data of the one symbol, data having a common index indicating their orders in the symbols can be stored at the same address in the RAM. As a result, symbol input and symbol output can be overlapped.
    • 在快速傅里叶变换中,必要的存储容量减少,从而降低成本。 根据由RAM地址发生器产生的RAM地址,通过蝶形运算单元对存储在RAM中的符号执行快速傅立叶变换。 RAM地址转换单元通过根据输入/输出位反向信号指定的频率进行位反转而将输入/输出虚拟地址转换为输入/输出实地址,并将蝶形运算虚拟地址转换为蝶形运算实际 通过根据蝶形运算位反向信号指定的频率进行位反转。 以这种方式,在随后的一个符号的输出数据之后的一个符号的输出数据和要存储在RAM中的另一个符号的输入数据之间,具有指示它们在符号中的顺序的公共索引的数据可以存储在相同的地址 在RAM中。 结果,符号输入和符号输出可以重叠。
    • 10. 发明申请
    • Receiving Apparatus, Receiving System Using Same, And Receiving Method Thereof
    • 接收装置,使用相同的接收系统及其接收方法
    • US20070274399A1
    • 2007-11-29
    • US11547282
    • 2004-11-18
    • Shunsuke SakaiYuji Nakai
    • Shunsuke SakaiYuji Nakai
    • H04N5/14
    • H04N5/4401H04N5/46H04N21/4305H04N21/4382H04N21/4622
    • A receiving apparatus (100) includes demodulation parts (101, 102) for receiving the respective one of received signals of broadast systems to output demodulated data and timing clocks synchronized with the respective demodulated data, a clock generating part (103) for outputting, to an A/V decoder (107), the two timing clocks from the demodulation parts (101, 102) as high-rate and low-rate timing clocks and for outputting a control signal for multiplexing the two demodulated data from the demodulation parts (101, 102), and a multiplexing part (104) for multiplexing, based on the control signal, the two demodulated data to output the multiplexed data to the A/V decoder (107). The A/V decoder (107) receives the multiplexed data and timing clocks from the receiving apparatus (100) to process the video/audio signals of each broadcast.
    • 一种接收装置(100),包括用于接收广播系统的接收信号中的相应一个的解调部分(101,102),以输出与各个解调数据同步的解调数据和定时时钟;时钟发生部分(103),用于输出 A / V解码器(107),来自解调部分(101,102)的两个定时时钟作为高速和低速定时时钟,并且用于输出用于从解调部分(101)复用两个解调数据的控制信号 ,102)和多路复用部分(104),用于基于控制信号多路复用两个解调数据,以将复用的数据输出到A / V解码器(107)。 A / V解码器(107)从接收装置(100)接收多路复用数据和定时时钟,以处理每个广播的视频/音频信号。