专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050265109A1 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20050265109A1
公开(公告)日：2005-12-01
申请号：US11135415
申请日：2005-05-24
申请人： Akira Goda , Mitsuhiro Noguchi , Minori Kajimoto , Yuji Takeuchi
发明人： Akira Goda , Mitsuhiro Noguchi , Minori Kajimoto , Yuji Takeuchi
IPC分类号： H01L27/10 , G11C8/00 , G11C8/10 , G11C16/04 , G11C16/08 , G11C16/10 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C8/10 , G11C16/0483 , G11C16/08 , G11C16/10 , H01L27/115 , H01L27/11521
摘要： A nonvolatile semiconductor memory includes: a memory cell array constituted by word lines, bit lines, and electrically erasable/rewritable memory cell transistors, which have respective tunnel insulating films and are arranged at the intersections of the word lines and the bit lines; and a word line transfer transistor, which is separated by an element isolation region, has a source diffusion layer, a channel region, a gate insulating film on the channel region, and a drain diffusion layer, and is connected to a word line and a gate electrode formed on the gate insulating film via a word line contact plug formed in the drain diffusion layer. The channel width of the word line transfer transistor is at least six times width of the word line contact plug, and the distance in a second direction between the word line contact plug and corresponding element isolation region is greater than distance in a first direction between the word line contact plug and corresponding element isolation region where, the first direction denotes a direction from the source diffusion layer towards the drain diffusion layer, and the second direction denotes a direction perpendicular to the first direction.
摘要翻译：非易失性半导体存储器包括：由字线，位线和电可擦除/可重写存储单元晶体管构成的存储单元阵列，其具有相应的隧道绝缘膜并且布置在字线和位线的交点处; 并且由元件隔离区隔开的字线传输晶体管在沟道区上具有源极扩散层，沟道区，栅极绝缘膜和漏极扩散层，并且连接到字线和栅极通过形成在漏极扩散层中的字线接触插塞形成在栅极绝缘膜上。字线传输晶体管的沟道宽度是字线接触插塞的至少六倍宽度，并且字线接触插塞和对应元件隔离区域之间的第二方向上的距离大于第二方向上的距离字线接触插塞和对应元件隔离区域，其中第一方向表示从源极扩散层朝向漏极扩散层的方向，第二方向表示与第一方向垂直的方向。

2. 发明授权

US07245534B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US07245534B2
公开(公告)日：2007-07-17
申请号：US11135415
申请日：2005-05-24
申请人： Akira Goda , Mitsuhiro Noguchi , Minori Kajimoto , Yuji Takeuchi
发明人： Akira Goda , Mitsuhiro Noguchi , Minori Kajimoto , Yuji Takeuchi
IPC分类号： G11C11/34
CPC分类号： G11C8/10 , G11C16/0483 , G11C16/08 , G11C16/10 , H01L27/115 , H01L27/11521
摘要： A nonvolatile semiconductor memory includes: a memory cell array constituted by word lines, bit lines, and electrically erasable/rewritable memory cell transistors, which have respective tunnel insulating films and are arranged at the intersections of the word lines and the bit lines; and a word line transfer transistor, which is separated by an element isolation region, has a source diffusion layer, a channel region, a gate insulating film on the channel region, and a drain diffusion layer, and is connected to a word line and a gate electrode formed on the gate insulating film via a word line contact plug formed in the drain diffusion layer. The channel width of the word line transfer transistor is at least six times width of the word line contact plug, and the distance in a second direction between the word line contact plug and corresponding element isolation region is greater than distance in a first direction between the word line contact plug and corresponding element isolation region where, the first direction denotes a direction from the source diffusion layer towards the drain diffusion layer, and the second direction denotes a direction perpendicular to the first direction.
摘要翻译：非易失性半导体存储器包括：由字线，位线和电可擦除/可重写存储单元晶体管构成的存储单元阵列，其具有相应的隧道绝缘膜并且布置在字线和位线的交点处; 并且由元件隔离区隔开的字线传输晶体管在沟道区上具有源极扩散层，沟道区，栅极绝缘膜和漏极扩散层，并且连接到字线和栅极通过形成在漏极扩散层中的字线接触插塞形成在栅极绝缘膜上。字线传输晶体管的沟道宽度是字线接触插塞的至少六倍宽度，并且字线接触插塞和对应元件隔离区域之间的第二方向上的距离大于第二方向上的距离字线接触插塞和对应元件隔离区域，其中第一方向表示从源极扩散层朝向漏极扩散层的方向，第二方向表示与第一方向垂直的方向。

3. 发明申请

US20100052032A1 Nonvolatile semiconductor memory and method for fabricating the same 有权
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20100052032A1
公开(公告)日：2010-03-04
申请号：US12588203
申请日：2009-10-07
申请人： Minori Kajimoto , Mitsuhiro Noguchi , Akira Goda
发明人： Minori Kajimoto , Mitsuhiro Noguchi , Akira Goda
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , H01L21/76838 , H01L27/115 , H01L27/11521
摘要： A nonvolatile semiconductor memory includes a first semiconductor layer; second semiconductor regions formed on the first semiconductor layer having device isolating regions extended in a column direction; a first interlayer insulator film formed above the first semiconductor layer; a lower conductive plug connected to the second semiconductor regions; a first interconnect extended in a row direction; a second interlayer insulator formed on the lower conductive plug and the first interlayer insulator film; an upper conductive plug; and a second interconnect formed on the second interlayer insulator contacting with the top of the upper conductive plug extended in the column direction.
摘要翻译：非易失性半导体存储器包括：第一半导体层; 形成在第一半导体层上的第二半导体区域，具有沿列方向延伸的器件隔离区域; 形成在所述第一半导体层上方的第一层间绝缘膜; 连接到第二半导体区域的下导电插塞; 沿行方向延伸的第一互连; 形成在下导电插塞和第一层间绝缘膜上的第二层间绝缘膜; 上导电插头; 以及形成在与沿列方向延伸的上导电插塞的顶部接触的第二层间绝缘体上的第二互连。

4. 发明授权

US07622762B2 Nonvolatile semiconductor memory and method for fabricating the same 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US07622762B2
公开(公告)日：2009-11-24
申请号：US12000396
申请日：2007-12-12
申请人： Minori Kajimoto , Mitsuhiro Noguchi , Akira Goda
发明人： Minori Kajimoto , Mitsuhiro Noguchi , Akira Goda
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , H01L21/76838 , H01L27/115 , H01L27/11521
摘要： A nonvolatile semiconductor memory includes a first semiconductor layer; second semiconductor regions formed on the first semiconductor layer having device isolating regions extended in a column direction; a first interlayer insulator film formed above the first semiconductor layer; a lower conductive plug connected to the second semiconductor regions; a first interconnect extended in a row direction; a second interlayer insulator formed on the lower conductive plug and the first interlayer insulator film; an upper conductive plug; and a second interconnect formed on the second interlayer insulator contacting with the top of the upper conductive plug extended in the column direction.
摘要翻译：非易失性半导体存储器包括：第一半导体层; 形成在第一半导体层上的第二半导体区域，具有沿列方向延伸的器件隔离区域; 形成在所述第一半导体层上方的第一层间绝缘膜; 连接到第二半导体区域的下导电插塞; 沿行方向延伸的第一互连; 形成在下导电插塞和第一层间绝缘膜上的第二层间绝缘膜; 上导电插头; 以及形成在与沿列方向延伸的上导电插塞的顶部接触的第二层间绝缘体上的第二互连。

5. 发明授权

US08253182B2 Nonvolatile semiconductor memory and method for fabricating the same 有权
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US08253182B2
公开(公告)日：2012-08-28
申请号：US12588203
申请日：2009-10-07
申请人： Minori Kajimoto , Mitsuhiro Noguchi , Akira Goda
发明人： Minori Kajimoto , Mitsuhiro Noguchi , Akira Goda
IPC分类号： H01L29/76
CPC分类号： H01L27/11568 , H01L21/76838 , H01L27/115 , H01L27/11521
摘要： A nonvolatile semiconductor memory includes a first semiconductor layer; second semiconductor regions formed on the first semiconductor layer having device isolating regions extended in a column direction; a first interlayer insulator film formed above the first semiconductor layer; a lower conductive plug connected to the second semiconductor regions; a first interconnect extended in a row direction; a second interlayer insulator formed on the lower conductive plug and the first interlayer insulator film; an upper conductive plug; and a second interconnect formed on the second interlayer insulator contacting with the top of the upper conductive plug extended in the column direction.
摘要翻译：非易失性半导体存储器包括：第一半导体层; 形成在第一半导体层上的第二半导体区域，具有沿列方向延伸的器件隔离区域; 形成在所述第一半导体层上方的第一层间绝缘膜; 连接到第二半导体区域的下导电插塞; 沿行方向延伸的第一互连; 形成在下导电插塞和第一层间绝缘膜上的第二层间绝缘膜; 上导电插头; 以及形成在与沿列方向延伸的上导电插塞的顶部接触的第二层间绝缘体上的第二互连。

6. 发明授权

US07326993B2 Nonvolatile semiconductor memory and method for fabricating the same 失效
公开(公告)号：US07326993B2
公开(公告)日：2008-02-05
申请号：US10890132
申请日：2004-07-14
申请人： Minori Kajimoto , Mitsuhiro Noguchi , Akira Goda
发明人： Minori Kajimoto , Mitsuhiro Noguchi , Akira Goda
IPC分类号： H01L29/788 , H01L23/522
CPC分类号： H01L27/11568 , H01L21/76838 , H01L27/115 , H01L27/11521
摘要： A nonvolatile semiconductor memory includes a first semiconductor layer; second semiconductor regions formed on the first semiconductor layer having device isolating regions extended in a column direction; a first interlayer insulator film formed above the first semiconductor layer; a lower conductive plug connected to the second semiconductor regions; a first interconnect extended in a row direction; a second interlayer insulator formed on the lower conductive plug and the first interlayer insulator film; an upper conductive plug; and a second interconnect formed on the second interlayer insulator contacting with the top of the upper conductive plug extended in the column direction.

7. 发明申请

US20050051831A1 Nonvolatile semiconductor memory and method for fabricating the same 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20050051831A1
公开(公告)日：2005-03-10
申请号：US10890132
申请日：2004-07-14
申请人： Minori Kajimoto , Mitsuhiro Noguchi , Akira Goda
发明人： Minori Kajimoto , Mitsuhiro Noguchi , Akira Goda
IPC分类号： H01L21/28 , H01L21/768 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L29/76 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , H01L21/76838 , H01L27/115 , H01L27/11521
摘要： A nonvolatile semiconductor memory includes a first semiconductor layer; second semiconductor regions formed on the first semiconductor layer having device isolating regions extended in a column direction; a first interlayer insulator film formed above the first semiconductor layer; a lower conductive plug connected to the second semiconductor regions; a first interconnect extended in a row direction; a second interlayer insulator formed on the lower conductive plug and the first interlayer insulator film; an upper conductive plug; and a second interconnect formed on the second interlayer insulator contacting with the top of the upper conductive plug extended in the column direction.
摘要翻译：非易失性半导体存储器包括：第一半导体层; 形成在第一半导体层上的第二半导体区域，具有沿列方向延伸的器件隔离区域; 形成在所述第一半导体层上方的第一层间绝缘膜; 连接到第二半导体区域的下导电插塞; 沿行方向延伸的第一互连; 形成在下导电插塞和第一层间绝缘膜上的第二层间绝缘膜; 上导电插头; 以及形成在与沿列方向延伸的上导电插塞的顶部接触的第二层间绝缘体上的第二互连。

8. 发明申请

US20080122098A1 Nonvolatile semiconductor memory and method for fabricating the same 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20080122098A1
公开(公告)日：2008-05-29
申请号：US12000396
申请日：2007-12-12
申请人： Minori Kajimoto , Mitsuhiro Noguchi , Akira Goda
发明人： Minori Kajimoto , Mitsuhiro Noguchi , Akira Goda
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L27/11568 , H01L21/76838 , H01L27/115 , H01L27/11521
摘要： A nonvolatile semiconductor memory includes a first semiconductor layer; second semiconductor regions formed on the first semiconductor layer having device isolating regions extended in a column direction; a first interlayer insulator film formed above the first semiconductor layer; a lower conductive plug connected to the second semiconductor regions; a first interconnect extended in a row direction; a second interlayer insulator formed on the lower conductive plug and the first interlayer insulator film; an upper conductive plug; and a second interconnect formed on the second interlayer insulator contacting with the top of the upper conductive plug extended in the column direction.
摘要翻译：非易失性半导体存储器包括：第一半导体层; 形成在第一半导体层上的第二半导体区域，具有沿列方向延伸的器件隔离区域; 形成在所述第一半导体层上方的第一层间绝缘膜; 连接到第二半导体区域的下导电插塞; 沿行方向延伸的第一互连; 形成在下导电插塞和第一层间绝缘膜上的第二层间绝缘膜; 上导电插头; 以及形成在与沿列方向延伸的上导电插塞的顶部接触的第二层间绝缘体上的第二互连。

9. 发明授权

US06958938B2 Data writing method for semiconductor memory device and semiconductor memory device 有权
标题翻译：半导体存储器件和半导体存储器件的数据写入方法
公开(公告)号：US06958938B2
公开(公告)日：2005-10-25
申请号：US11007461
申请日：2004-12-09
申请人： Mitsuhiro Noguchi , Akira Goda , Yuji Takeuchi
发明人： Mitsuhiro Noguchi , Akira Goda , Yuji Takeuchi
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/12 , G11C16/34 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/3445 , G11C16/0416 , G11C16/0483 , G11C16/12 , G11C16/3468
摘要： A data writing method for a semiconductor memory device includes writing data into the first memory cell, rewriting the data into the first memory cell when an insufficiency of the data of the first memory cell is determined as a result of verifying the data of the first memory cell at one first reference threshold voltage, writing data into the second memory cell following writing the data into the first memory cell, and rewriting the data into the first memory cell following writing the data into the second memory cell when an insufficiency of the data of the first memory cell is determined as a result of verifying the data of the first memory cell at one second reference threshold voltage. The first reference threshold voltage is set to be different from the second reference threshold voltage.
摘要翻译：半导体存储器件的数据写入方法包括将数据写入第一存储单元，当确定第一存储单元的数据不足时，将数据重新写入第一存储器单元作为验证第一存储器的数据的结果在一个第一参考阈值电压下，将数据写入第一存储单元之后，将数据写入第二存储单元，并且当数据不足时将数据写入第二存储单元中作为第一存储单元的数据在一秒钟的参考阈值电压下进行验证的结果来确定第一存储单元。第一参考阈值电压被设置为不同于第二参考阈值电压。

10. 发明申请

US20050157558A1 DATA WRITING METHOD FOR SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：用于半导体存储器件和半导体存储器件的数据写入方法
公开(公告)号：US20050157558A1
公开(公告)日：2005-07-21
申请号：US11007461
申请日：2004-12-09
申请人： Mitsuhiro Noguchi , Akira Goda , Yuji Takeuchi
发明人： Mitsuhiro Noguchi , Akira Goda , Yuji Takeuchi
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/12 , G11C16/34 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/3445 , G11C16/0416 , G11C16/0483 , G11C16/12 , G11C16/3468
摘要： A data writing method for a semiconductor memory device includes writing data into the first memory cell, rewriting the data into the first memory cell when an insufficiency of the data of the first memory cell is determined as a result of verifying the data of the first memory cell at one first reference threshold voltage, writing data into the second memory cell following writing the data into the first memory cell, and rewriting the data into the first memory cell following writing the data into the second memory cell when an insufficiency of the data of the first memory cell is determined as a result of verifying the data of the first memory cell at one second reference threshold voltage. The first reference threshold voltage is set to be different from the second reference threshold voltage.
摘要翻译：半导体存储器件的数据写入方法包括将数据写入第一存储单元，当确定第一存储单元的数据不足时，将数据重新写入第一存储器单元作为验证第一存储器的数据的结果在一个第一参考阈值电压下，将数据写入第一存储单元之后，将数据写入第二存储单元，并且当数据不足时将数据写入第二存储单元中作为第一存储单元的数据在一秒钟的参考阈值电压下进行验证的结果来确定第一存储单元。第一参考阈值电压被设置为不同于第二参考阈值电压。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式