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1. 发明授权

US5267097A Information transfer control system having rotary storage unit which uses a pseudo address mark 失效
标题翻译：具有使用伪地址标记的旋转存储单元的信息传送控制系统
公开(公告)号：US5267097A
公开(公告)日：1993-11-30
申请号：US944820
申请日：1992-09-14
申请人： Akihito Ogino , Michio Miyazaki , Kiyoshi Hisano
发明人： Akihito Ogino , Michio Miyazaki , Kiyoshi Hisano
IPC分类号： G11B20/10 , G11B27/00 , G11B27/30 , G11B5/09
CPC分类号： G11B20/10 , G11B27/005 , G11B27/3027 , G11B2220/20
摘要： When a positioning operation of a head on a track of a disk including a target record is completed, information is read out from the track of the disk and stored in a buffer memory without waiting a read command from a host side controller. A transfer operation of the target record of the information from the buffer memory to the controller is performed when the controller is not busy and generates the read command. A transfer rate of the record from the buffer memory to the controller is made faster than a read rate of the information from a disk or a write rate into the buffer memory, so that a nominal transfer rate of an entire system is increased without changing the read or write rate.
摘要翻译：当头部在包括目标记录的盘的轨道上的定位操作完成时，从盘的轨迹读出信息并将其存储在缓冲存储器中，而不用等待来自主机侧控制器的读命令。当控制器不忙并且产生读取命令时，执行从缓冲存储器到控制器的信息的目标记录的传送操作。从缓冲存储器到控制器的记录的传送速率比从盘的信息或写入速率到缓冲存储器的读取速度更快，使得整个系统的标称传送速率增加而不改变读写速率。

2. 发明授权

US5606684A On-line dumping system and disk sub-system 失效
标题翻译：在线倾卸系统和磁盘子系统
公开(公告)号：US5606684A
公开(公告)日：1997-02-25
申请号：US319775
申请日：1994-10-07
申请人： Toshio Nakano , Masafumi Nozawa , Kiyoshi Hisano , Akihito Ogino , Akira Kurano , Hiroyuki Kitajima , Akihiko Togawa
发明人： Toshio Nakano , Masafumi Nozawa , Kiyoshi Hisano , Akihito Ogino , Akira Kurano , Hiroyuki Kitajima , Akihiko Togawa
IPC分类号： G06F3/06 , G06F12/00 , G06F13/20 , G06F13/00
CPC分类号： G06F3/0601 , G06F13/20 , G06F2003/0691 , G06F2003/0692
摘要： A buffer memory capable of storing contents of a plurality of tracks of a disk volume is provided in a disk controller or a disk drive, and in dump processing requested by a higher rank unit (CPU) to the disk controller, the data is immediately transferred from the buffer memory if the data to be dumped is present in the buffer memory, and if the data to be dumped is not present in the buffer memory, dump prefetching into the buffer memory is started and the execution of the dump processing is interrupted so that an on-line input/output operation other than the dump processing is accepted. When the dump prefetching into the buffer memory is over, the interrupted dump processing is resumed.
摘要翻译：在磁盘控制器或磁盘驱动器中提供能够存储磁盘卷的多个磁道的内容的缓冲存储器，并且在由高级单元（CPU）向磁盘控制器请求的转储处理中，立即传送数据如果缓冲存储器中存在要转储的数据，则从缓冲存储器中读取缓冲存储器中的数据，如果缓存器中不存在要转储的数据，则转储预取到缓冲存储器中，转储处理的执行中断接受转储处理以外的在线输入/输出操作。当转储预取到缓冲存储器中时，恢复中断的转储处理。

3. 发明授权

US5410666A On-line dumping system and disk sub system 失效
标题翻译：在线倾卸系统和磁盘子系统
公开(公告)号：US5410666A
公开(公告)日：1995-04-25
申请号：US583311
申请日：1990-09-17
申请人： Toshio Nakano , Masafumi Nozawa , Kiyoshi Hisano , Akihito Ogino , Akira Kurano , Hiroyuki Kitajima , Akihiko Togawa
发明人： Toshio Nakano , Masafumi Nozawa , Kiyoshi Hisano , Akihito Ogino , Akira Kurano , Hiroyuki Kitajima , Akihiko Togawa
IPC分类号： G06F3/06 , G06F12/00 , G06F13/20 , G06F13/00
CPC分类号： G06F3/0601 , G06F13/20 , G06F2003/0691 , G06F2003/0692
摘要： A buffer memory capable of storing contents of a plurality of tracks of a disk volume is provided in a disk controller or a disk drive, and in dump processing requested by a higher rank unit (CPU) to the disk controller, the data is immediately transferred from the buffer memory if the data to be dumped is present in the buffer memory, and if the data to be dumped is not present in the buffer memory, dump prefetching into the buffer memory is started and the execution of the dump processing is interrupted so that an on-line input/output operation other than the dump processing is accepted. When the dump prefetching into the buffer memory is over, the interrupted dump processing is resumed.
摘要翻译：在磁盘控制器或磁盘驱动器中提供能够存储磁盘卷的多个磁道的内容的缓冲存储器，并且在由高级单元（CPU）向磁盘控制器请求的转储处理中，立即传送数据如果缓冲存储器中存在要转储的数据，则从缓冲存储器中读取缓冲存储器中的数据，如果缓存器中不存在要转储的数据，则转储预取到缓冲存储器中，转储处理的执行中断接受转储处理以外的在线输入/输出操作。当转储预取到缓冲存储器中时，恢复中断的转储处理。

4. 发明授权

US4800483A Method and system for concurrent data transfer disk cache system 失效
标题翻译：并发数据传输磁盘缓存系统的方法和系统
公开(公告)号：US4800483A
公开(公告)日：1989-01-24
申请号：US56355
申请日：1987-05-28
申请人： Akira Yamamoto , Toru Nishigaki , Akira Kurano , Kiyoshi Hisano , Yoshiro Shiroyanagi
发明人： Akira Yamamoto , Toru Nishigaki , Akira Kurano , Kiyoshi Hisano , Yoshiro Shiroyanagi
IPC分类号： G06F13/10 , G06F12/08 , G06F13/12 , G06F13/00
CPC分类号： G06F13/122 , G06F12/0866 , G06F12/0862
摘要： The present invention relates to a computer system having a disk cache unit between a disk unit and the main storage unit. Ordinarily, the data transfer processing is carried out between the disk unit and the disk cache unit and between the disk cache unit and the main storage unit in this case under control of a director. The present invention is characterized by enabling these two data transfer operations to be executed in parallel and to prevent the director from becoming the bottleneck of the processing due to the concentrated processing requests. For this purpose, the present invention provides for a data transfer between the disk cache unit and a disk unit while a data transfer is taking place between the main storage unit and the disk cache unit.
摘要翻译：本发明涉及一种在盘单元和主存储单元之间具有盘缓存单元的计算机系统。通常，在这种情况下，在导向器的控制下，在盘单元和盘高速缓存单元之间以及盘缓存单元和主存储单元之间执行数据传送处理。本发明的特征在于能够并行地执行这两个数据传送操作，并且防止由于集中的处理请求引导器成为处理的瓶颈。为此，本发明提供了在主存储单元和盘高速缓存单元之间进行数据传输的同时在盘缓存单元和盘单元之间的数据传送。

5. 发明授权

US4870565A Parallel transfer type director means 失效
标题翻译：并行传输型导向装置
公开(公告)号：US4870565A
公开(公告)日：1989-09-26
申请号：US322119
申请日：1989-03-13
申请人： Akira Yamamoto , Toru Nishigaki , Akira Kurano , Kiyoshi Hisano , Yoshiro Shiroyana
发明人： Akira Yamamoto , Toru Nishigaki , Akira Kurano , Kiyoshi Hisano , Yoshiro Shiroyana
IPC分类号： G06F13/10 , G06F12/08 , G06F13/12
CPC分类号： G06F13/122 , G06F12/0866 , G06F12/0862
摘要： A computer system having a disk cache unit between a disk unit and the main storage unit. Ordinarily, the data transfer processing is carried out between the disk unit and the disk cache unit and between the disk cache unit and the main storage unit in this case. The present invention is characterized by enabling these two data transfer operations to be executed in parallel and to prevent a director from becoming the bottleneck of the processing due to the concentrated processing requests. For this purpose, the present invention provides for conducting a data transfer between the disk cache unit and a disk unit while a data transfer is taking place between the main storage unit and the disk cache unit. The director is configured, for example, with two data transfer controlling systems and two data transfer units for carrying out data transfer according to instructions for the two data transfer controlling systems.
摘要翻译：一种在盘单元和主存储单元之间具有盘缓存单元的计算机系统。通常，在这种情况下，在盘单元和盘缓存单元之间以及盘高速缓存单元和主存储单元之间执行数据传送处理。本发明的特征在于能够并行地执行这两个数据传送操作，并且防止由于集中的处理请求导致控制器成为处理的瓶颈。为此，本发明提供了在主存储单元和磁盘高速缓存单元之间进行数据传输的同时，在磁盘高速缓存单元和磁盘单元之间进行数据传送。导向器例如配置有两个数据传输控制系统和两个用于根据两个数据传输控制系统的指令执行数据传输的数据传输单元。

6. 发明授权

US5335327A External memory control techniques with multiprocessors improving the throughput of data between a hierarchically upper processing unit and an external memory with efficient use of a cache memory 失效
标题翻译：具有多处理器的外部存储器控制技术通过高效地使用高速缓冲存储器来提高层级上位处理单元和外部存储器之间的数据吞吐量
公开(公告)号：US5335327A
公开(公告)日：1994-08-02
申请号：US38523
申请日：1993-03-29
申请人： Kiyoshi Hisano , Ken Hirashima , Hiroyuki Kurosawa , Kenji Kubota , Shuji Sugimoto
发明人： Kiyoshi Hisano , Ken Hirashima , Hiroyuki Kurosawa , Kenji Kubota , Shuji Sugimoto
IPC分类号： G06F3/06 , G06F12/08 , G06F13/00 , G06F13/12 , G06F13/14 , G06F13/38
CPC分类号： G06F12/0866
摘要： A disk unit control apparatus (DKC) comprises a cache memory provided between a CPU and an external memory (DKU) storing the information exchanged with the CPU, the cache memory holding temporarily copies of the information stored in the DKU. A request from the CPU for access to the information stored in the DKU is met as far as possible by use of the information held in the cache memory. First transfer routes of information between the CPU and the cache memory is greater in number than second transfer routes of information between the cache memory and the DKU. This makes it possible that even when direct accesses to the DKU in the same number as the second transfer routes occur in each of the first transfer route, accesses to the cache memory which may arise from other CPUs are capable of being effected through the remaining ones of the first transfer routes. As a result, a cache memory accessible with high speed is obtained, and the utilization efficiency of the data stored in the cache memory is substantially improved, improving the data throughput between the CPU and the DKU.
摘要翻译：盘单元控制装置（DKC）包括设置在CPU和存储与CPU交换的信息的外部存储器（DKU）之间的高速缓冲存储器，高速缓存存储器暂时保存存储在DKU中的信息。通过使用保存在高速缓冲存储器中的信息，可以尽可能地满足来自CPU访问存储在DKU中的信息的请求。在CPU和高速缓冲存储器之间的第一个信息传输路径的数量大于缓存和DKU之间的第二个传输信息路由。这使得即使在与第二传送路由相同数量的DKU的直接访问发生在第一传送路由的每一个中的情况下，也可能通过剩余的对其他CPU的访问到高速缓冲存储器的第一批转运路线。结果，可以获得高速存取的高速缓冲存储器，并且显着地改善了存储在高速缓冲存储器中的数据的利用效率，从而提高了CPU与DKU之间的数据吞吐量。

7. 发明授权

US5241640A Disk unit with processors which detect cache status and control port selection for optimizing utilization of cache interfacing host and external memory 失效
标题翻译：具有处理器的磁盘单元，用于检测缓存状态和控制端口选择，以优化高速缓存接口主机和外部存储器的使用
公开(公告)号：US5241640A
公开(公告)日：1993-08-31
申请号：US418659
申请日：1989-10-10
申请人： Kiyoshi Hisano , Ken Hirashima , Hiroyuki Kurosawa , Kenji Kubota , Shuji Sugimoto
发明人： Kiyoshi Hisano , Ken Hirashima , Hiroyuki Kurosawa , Kenji Kubota , Shuji Sugimoto
IPC分类号： G06F3/06 , G06F12/08
CPC分类号： G06F12/0866
摘要： A disk unit control apparatus (DKC) comprises a cache memory provided between a CPU and an external memory (DKU) storing the information exchanged with the CPU, the cache memory holding temporarily copies of the information stored in the DKU. A request from the CPU for access to the information stored in the DKU is met as far as possible by use of the information held in the cache memory. First transfer routes of information between the CPU and the cache memory is greater in number than second transfer routes of information between the cache memory and the DKU. This makes it possible that even when direct accesses to the DKU in the same number as the second transfer routes occur in each of the first transfer route, acesses to the cache memory which may arise from other CPUs are capable of being effected through the remaining ones of the first transfer routes. As a result, a cache memory accessible with high speed is obtained, and the utilization efficiency of the data stored in the cache memory is substantially improved, improving the data throughput between the CPU and the DKU.
摘要翻译：盘单元控制装置（DKC）包括设置在CPU和存储与CPU交换的信息的外部存储器（DKU）之间的高速缓冲存储器，高速缓存存储器暂时保存存储在DKU中的信息。通过使用保存在高速缓冲存储器中的信息，可以尽可能地满足来自CPU访问存储在DKU中的信息的请求。在CPU和高速缓冲存储器之间的第一个信息传输路径的数量大于缓存和DKU之间的第二个传输信息路由。这使得即使在与第二传送路由相同数量的DKU的直接访问在第一传送路由的每一个中发生的情况下，也可以通过剩余的那些对其他CPU可能产生的高速缓冲存储器的访问的第一批转运路线。结果，可以获得高速存取的高速缓冲存储器，并且显着地改善了存储在高速缓冲存储器中的数据的利用效率，从而提高了CPU与DKU之间的数据吞吐量。

8. 发明授权

US5226157A Backup control method and system in data processing system using identifiers for controlling block data transfer 失效
标题翻译：使用标识符控制块数据传输的数据处理系统中的备份控制方法和系统
公开(公告)号：US5226157A
公开(公告)日：1993-07-06
申请号：US318006
申请日：1989-03-02
申请人： Toshio Nakano , Masafumi Nozawa , Akira Kurano , Kiyoshi Hisano , Masayuki Hoshino
发明人： Toshio Nakano , Masafumi Nozawa , Akira Kurano , Kiyoshi Hisano , Masayuki Hoshino
IPC分类号： G06F12/16 , G06F11/14 , G06F12/00
CPC分类号： G06F11/1451 , G06F11/1466
摘要： In a data processing system having a first external memory, a second external memory, and a control memory for storing information on data renewals in the first external memory, a system and a method provide for back-up operations in parallel with ordinary data processing, including dump processing in which renewed data parts in the first external memory are copied as backup data into the second external memory with reference to the contents of the control memory. The method provides the step of storing into the control memory first identifier information for identifying areas of the first external memory where data items were renewed; the step of storing into the control memory second identifier information for identifying areas of the first external memory where data items were renewed during the dump processing; and the step of erasing at completion of the dump processing the first identifier information items except those which identify the same areas as identified by the second identifier information items. Thus, ordinary job processing and the renewals of the data items of the first external memory can be performed even in the course of the data dumping processing.

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