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1. 发明授权

US07750400B2 Integrated circuit modeling, design, and fabrication based on degradation mechanisms 有权
标题翻译：基于降解机制的集成电路建模，设计和制造
公开(公告)号：US07750400B2
公开(公告)日：2010-07-06
申请号：US12192850
申请日：2008-08-15
申请人： Ajit Shanware , Srikanth Krishnan
发明人： Ajit Shanware , Srikanth Krishnan
IPC分类号： H01L21/00
CPC分类号： H01L27/092 , H01L27/0207
摘要： An integrated circuit (IC) includes at least a first complementary MOS (CMOS) circuit, the first CMOS circuit comprising one or more first n-channel MOS (NMOS) transistors and one or more first p-channel MOS (PMOS) transistors, where the first NMOS transistors and the first PMOS transistors are arranged in the first CMOS circuit to drive at least a first common node of the first CMOS circuit. An average of the effective gate channel lengths of the first NMOS transistors (first NMOS average length) is at least 2% greater than an average of the effective gate channel lengths of the first PMOS transistors (first PMOS average length).
摘要翻译：集成电路（IC）至少包括第一互补MOS（CMOS）电路，第一CMOS电路包括一个或多个第一n沟道MOS（NMOS）晶体管和一个或多个第一p沟道MOS（PMOS）晶体管，其中第一NMOS晶体管和第一PMOS晶体管布置在第一CMOS电路中以驱动第一CMOS电路的至少第一公共节点。第一NMOS晶体管的有效栅极沟道长度的平均值（第一NMOS平均长度）比第一PMOS晶体管的有效栅极沟道长度的平均值（第一PMOS平均长度）至少大2％。

2. 发明申请

US20100038683A1 INTEGRATED CIRCUIT MODELING, DESIGN, AND FABRICATION BASED ON DEGRADATION MECHANISMS 有权
标题翻译：基于降解机制的集成电路建模，设计和制造
公开(公告)号：US20100038683A1
公开(公告)日：2010-02-18
申请号：US12192850
申请日：2008-08-15
申请人： Ajit Shanware , Srikanth Krishnan
发明人： Ajit Shanware , Srikanth Krishnan
IPC分类号： H01L29/94 , G06F17/00 , H01L21/66
CPC分类号： H01L27/092 , H01L27/0207
摘要： An integrated circuit (IC) includes at least a first complementary MOS (CMOS) circuit, the first CMOS circuit comprising one or more first n-channel MOS (NMOS) transistors and one or more first p-channel MOS (PMOS) transistors, where the first NMOS transistors and the first PMOS transistors are arranged in the first CMOS circuit to drive at least a first common node of the first CMOS circuit. An average of the effective gate channel lengths of the first NMOS transistors (first NMOS average length) is at least 2% greater than an average of the effective gate channel lengths of the first PMOS transistors (first PMOS average length).
摘要翻译：集成电路（IC）至少包括第一互补MOS（CMOS）电路，第一CMOS电路包括一个或多个第一n沟道MOS（NMOS）晶体管和一个或多个第一p沟道MOS（PMOS）晶体管，其中第一NMOS晶体管和第一PMOS晶体管布置在第一CMOS电路中以驱动第一CMOS电路的至少第一公共节点。第一NMOS晶体管的有效栅极沟道长度的平均值（第一NMOS平均长度）比第一PMOS晶体管的有效栅极沟道长度的平均值（第一PMOS平均长度）至少大2％。

3. 发明授权

US08138829B2 Segmented power amplifier with varying segment activation 有权
标题翻译：分段功率放大器，具有不同的段激活
公开(公告)号：US08138829B2
公开(公告)日：2012-03-20
申请号：US12789342
申请日：2010-05-27
申请人： Vijay Kumar Reddy , Srikanth Krishnan , Brian P Ginsburg , Srinath Mathur Ramaswamy , Chih-Ming Hung
发明人： Vijay Kumar Reddy , Srikanth Krishnan , Brian P Ginsburg , Srinath Mathur Ramaswamy , Chih-Ming Hung
IPC分类号： H03F1/14
CPC分类号： H03F3/211 , H03F1/0277 , H03F1/56 , H03F3/193 , H03F3/245 , H03F3/72 , H03F2200/105 , H03F2200/366 , H03F2200/451 , H03F2203/21178 , H03F2203/7215 , H03F2203/7236
摘要： Various apparatuses and methods for varying segment activation in a segmented power amplifier are disclosed herein. For example, some embodiments provide a power amplifier including an input, an output, a plurality of amplifier segments and a controller. The amplifier segments are connected in parallel between the input and the output and are adapted to be activated and inactivated. The power level at the output may be controlled by changing a number of the amplifier segments that are activated concurrently. The controller is connected to the amplifier segments and is adapted to vary which of the amplifier segments are activated to arrive at a selected number of activated amplifier segments.
摘要翻译：本文公开了用于在分段功率放大器中改变段激活的各种装置和方法。例如，一些实施例提供了包括输入，输出，多个放大器段和控制器的功率放大器。放大器段在输入和输出之间并联连接，并适于被激活和失活。可以通过改变同时激活的放大器段的数量来控制输出端的功率电平。控制器连接到放大器段，并且适于改变哪个放大器段被激活以到达选定数量的激活的放大器段。

4. 发明授权

US07218132B2 System and method for accurate negative bias temperature instability characterization 有权
公开(公告)号：US07218132B2
公开(公告)日：2007-05-15
申请号：US11290077
申请日：2005-11-30
申请人： Anand T. Krishnan , Srikanth Krishnan , Vijay Reddy , Cathy Chancellor
发明人： Anand T. Krishnan , Srikanth Krishnan , Vijay Reddy , Cathy Chancellor
IPC分类号： G01R31/26
CPC分类号： G01R31/2621
摘要： Methods and systems are provided for characterizing the negative temperature bias instability of a transistor. A bias voltage is maintained at a drain terminal of the transistor during a test period. A stress voltage is maintained at a gate terminal of the transistor during the test period, such that the stress voltage is applied concurrently with the bias voltage. At least one characteristic of the transistor is measured at periodic intervals during the stress period to determine a degradation of the at least one characteristic caused by the stress voltage until a termination event occurs.

5. 发明授权

US6117745A Bistable fuse by amorphization of polysilicon 有权
标题翻译：双稳态保险丝通过多晶硅非晶化
公开(公告)号：US6117745A
公开(公告)日：2000-09-12
申请号：US148260
申请日：1998-09-04
申请人： Srikanth Krishnan
发明人： Srikanth Krishnan
IPC分类号： H01L23/525 , H01L21/20
CPC分类号： H01L23/5256 , H01L2924/0002
摘要： An embodiment of the instant invention is a method of substantially isolating an electrical device over a semiconductor substrate from a structure which collects charge, the method comprising the steps of: forming an insulating layer (layer 304) on the substrate; forming a conductive layer (layer 306) on the insulating layer; incorporating at least one element (element 310) into portions of the conductive layer so as to render that portion the conductive layer more resistive; and wherein the portion of the conductive layer which has been rendered more resistive (region 312) is rendered conductive after one or more charging events by subjecting the portion of the conductive layer to an elevated temperature. Preferably, the element is comprised of an element selected from the group comprised of: As, P, N, Ar, Si, H, B, Ge, C, Sb, F, Cl, O, any noble element, and any combination thereof and their isotopes. The structure which collects charge is, preferably, a conductive structure (structure 11) which collects charge during plasma processing.
摘要翻译：本发明的一个实施例是一种从收集电荷的结构基本上隔离半导体衬底上的电子器件的方法，该方法包括以下步骤：在衬底上形成绝缘层（层304）; 在绝缘层上形成导电层（层306）; 将至少一个元件（元件310）结合到导电层的部分中，以使该部分导电层更具阻性; 并且其中通过使导电层的一部分经历升高的温度，在一个或多个充电事件之后，已经变得更加电阻（区域312）的导电层的部分变得导电。优选地，元素由选自As，P，N，Ar，Si，H，B，Ge，C，Sb，F，Cl，O，任何贵金属及其任何组合的元素组成及其同位素。收集电荷的结构优选地是在等离子体处理期间收集电荷的导电结构（结构11）。

6. 发明申请

US20100164533A1 METHOD AND APPARATUS FOR EVALUATING THE EFFECTS OF STRESS ON AN RF OSCILLATOR 有权
标题翻译：用于评估应力在RF振荡器上的影响的方法和装置
公开(公告)号：US20100164533A1
公开(公告)日：2010-07-01
申请号：US12352795
申请日：2009-01-13
申请人： Andrew Marshall , Srikanth Krishnan
发明人： Andrew Marshall , Srikanth Krishnan
IPC分类号： G01R27/26 , G01R31/26
CPC分类号： G01R31/2617 , G01R31/2824
摘要： Apparatus and methods are disclosed for evaluating degradation of a transistor in a cross coupled pair of an RF oscillator independently. A MOS device can be coupled between a separated center-tap inductor. By appropriately sizing the MOS device and turning the MOS device on during operation of RF oscillator, a good contact can again be made that allows the oscillator to operate at design performance. By turning the MOS device off, the supplies can be separates such that I-V characteristics of both transistors of the cross-coupled pair may be obtained.
摘要翻译：公开了用于评估RF振荡器的交叉耦合对中的晶体管的劣化的装置和方法。 MOS器件可以耦合在分离的中心抽头电感器之间。通过在RF振荡器工作期间适当调整MOS器件并使MOS器件导通，可以再次进行良好的接触，使得振荡器能够以设计性能工作。通过关闭MOS器件，可以分离电源，使得可以获得交叉耦合对的两个晶体管的I-V特性。

7. 发明授权

US07262468B2 Method and system for reducing charge damage in silicon-on-insulator technology 有权
标题翻译：绝缘体上硅技术减少电荷损伤的方法和系统
公开(公告)号：US07262468B2
公开(公告)日：2007-08-28
申请号：US10035606
申请日：2001-12-28
申请人： James D. Gallia , Srikanth Krishnan , Anand T. Krishnan
发明人： James D. Gallia , Srikanth Krishnan , Anand T. Krishnan
IPC分类号： H01L23/62 , H01L27/01 , H01L27/02 , H01L31/0392
CPC分类号： H01L27/1203
摘要： According to one embodiment of the invention, a silicon-on-insulator device includes an insulative layer formed overlying a substrate and a source and drain region formed overlying the insulative layer. The source region and the drain region comprise a material having a first conductivity type. A body region is disposed between the source region and the drain region and overlying the insulative layer. The body region comprises a material having a second conductivity type. A gate insulative layer overlies the body region. This device also includes a gate region overlying the gate insulative layer. The device also includes a diode circuit conductively coupled to the source region and a conductive connection coupling the gate region to the diode circuit.
摘要翻译：根据本发明的一个实施例，绝缘体上硅器件包括覆盖在衬底上的绝缘层和形成在绝缘层上的源极和漏极区。源区和漏区包括具有第一导电类型的材料。体区域设置在源极区域和漏极区域之间并且覆盖绝缘层。身体区域包括具有第二导电类型的材料。门绝缘层覆盖身体区域。该器件还包括覆盖栅极绝缘层的栅极区域。该器件还包括一个二极管电路，该二极管电路与该源极区域导电耦合，一个将该栅极区域耦合到该二极管电路的导电连接。

8. 发明授权

US07212023B2 System and method for accurate negative bias temperature instability characterization 有权
标题翻译：准确的负偏压温度不稳定性表征的系统和方法
公开(公告)号：US07212023B2
公开(公告)日：2007-05-01
申请号：US10935375
申请日：2004-09-07
申请人： Anand T. Krishnan , Srikanth Krishnan , Vijay Reddy , Cathy Chancellor
发明人： Anand T. Krishnan , Srikanth Krishnan , Vijay Reddy , Cathy Chancellor
IPC分类号： G01R31/26
CPC分类号： G01R31/2621
摘要： Methods and systems are provided for characterizing the negative temperature bias instability of a transistor. A bias voltage is maintained at a drain terminal of the transistor during a test period. A stress voltage is maintained at a gate terminal of the transistor during the test period, such that the stress voltage is applied concurrently with the bias voltage. At least one characteristic of the transistor is measured at periodic intervals during the stress period to determine a degradation of the at least one characteristic caused by the stress voltage until a termination event occurs.
摘要翻译：提供了用于表征晶体管的负温度偏置不稳定性的方法和系统。在测试期间，晶体管的漏极端子保持偏置电压。在测试期间，在晶体管的栅极端子处保持应力电压，使得与偏置电压同时施加应力电压。在应力周期期间以周期性间隔测量晶体管的至少一个特性，以确定由应力电压引起的直到终止事件发生的至少一个特性的劣化。

9. 发明授权

US07031163B2 Mechanical cooling fin for interconnects 有权
标题翻译：用于互连的机械散热片
公开(公告)号：US07031163B2
公开(公告)日：2006-04-18
申请号：US10688288
申请日：2003-10-17
申请人： Ki-Don Lee , Srikanth Krishnan , William R. Hunter
发明人： Ki-Don Lee , Srikanth Krishnan , William R. Hunter
IPC分类号： H05K7/20 , H01L23/34
CPC分类号： H01L23/367 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, an integrated circuit includes an electrically active interconnect line within a dielectric layer having a top and bottom surface, the bottom surface of the dielectric layer being coupled to the top surface of a substrate underlying the dielectric layer. The dielectric layer has horizontally arranged heat dissipating layers. An electrically inactive conductor or cooling fin is located within the dielectric layer at a heat dissipating layer below and closer to the substrate than said active interconnect line. The electrically inactive conductor is coupled to said electrically active interconnect line as an extensions of electrically active interconnect line to dissipate heat therefrom.
摘要翻译：在一个实施例中，集成电路包括在具有顶表面和底表面的电介质层内的电活动互连线，介电层的底表面耦合到介电层下面的衬底的顶表面。电介质层具有水平布置的散热层。电绝缘导体或冷却翅片位于电介质层内的位于比所述有源互连线下方更靠近衬底的散热层处。电不活动的导体被耦合到所述电活动互连线作为电活动互连线的延伸部分以从其中散发热量。

10. 发明申请

US20060049842A1 System and method for accurate negative bias temperature instability characterization 有权
标题翻译：准确的负偏压温度不稳定性表征的系统和方法
公开(公告)号：US20060049842A1
公开(公告)日：2006-03-09
申请号：US10935375
申请日：2004-09-07
申请人： Anand Krishnan , Srikanth Krishnan , Vijay Reddy , Cathy Chancellor
发明人： Anand Krishnan , Srikanth Krishnan , Vijay Reddy , Cathy Chancellor
IPC分类号： G01R31/26
CPC分类号： G01R31/2621
摘要： Methods and systems are provided for characterizing the negative temperature bias instability of a transistor. A bias voltage is maintained at a drain terminal of the transistor during a test period. A stress voltage is maintained at a gate terminal of the transistor during the test period, such that the stress voltage is applied concurrently with the bias voltage. At least one characteristic of the transistor is measured at periodic intervals during the stress period to determine a degradation of the at least one characteristic caused by the stress voltage until a termination event occurs.
摘要翻译：提供了用于表征晶体管的负温度偏置不稳定性的方法和系统。在测试期间，晶体管的漏极端子保持偏置电压。在测试期间，在晶体管的栅极端子处保持应力电压，使得与偏置电压同时施加应力电压。在应力周期期间以周期性间隔测量晶体管的至少一个特性，以确定由应力电压引起的直到终止事件发生的至少一个特性的劣化。

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