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1. 发明公开

US20240085964A1 OPERATING VOLTAGE ADJUSTMENT FOR AGING CIRCUITS 审中-公开
公开(公告)号：US20240085964A1
公开(公告)日：2024-03-14
申请号：US18515131
申请日：2023-11-20
申请人： Advanced Micro Devices, Inc.
发明人： Sriram Sambamurthy , Sriram Sundaram , Indrani Paul , Larry David Hewitt , Anil Harwani , Aaron Joseph Grenat , Dana Glenn Lewis , Leonardo Piga , Wonje Choi , Karthik Rao
IPC分类号： G06F1/28 , G01R31/40 , G06F1/30
CPC分类号： G06F1/28 , G01R31/40 , G06F1/30
摘要： A system and method for updating power supply voltages due to variations from aging are described. A functional unit includes a power supply monitor capable of measuring power supply variations in a region of the functional unit. An age counter measures an age of the functional unit. A control unit notifies the power supply monitor to measure an operating voltage reference. When the control unit receives a measured operating voltage reference, the control unit determines an updated age of the region different from the current age based on the measured operating voltage reference. The control unit updates the age counter with the corresponding age, which is younger than the previous age in some cases due to the region not experiencing predicted stress and aging. The control unit is capable of determining a voltage adjustment for the operating voltage reference based on an age indicated by the age counter.

2. 发明申请

US20220100249A1 OPERATING VOLTAGE ADJUSTMENT FOR AGING CIRCUITS 有权
公开(公告)号：US20220100249A1
公开(公告)日：2022-03-31
申请号：US17127681
申请日：2020-12-18
申请人： Advanced Micro Devices, Inc.
发明人： Sriram Sambamurthy , Sriram Sundaram , Indrani Paul , Larry David Hewitt , Anil Harwani , Aaron Joseph Grenat , Dana Glenn Lewis , Leonardo Piga , Wonje Choi , Karthik Rao
IPC分类号： G06F1/28 , G06F1/30 , G01R31/40
摘要： A system and method for updating power supply voltages due to variations from aging are described. A functional unit includes a power supply monitor capable of measuring power supply variations in a region of the functional unit. An age counter measures an age of the functional unit. A control unit notifies the power supply monitor to measure an operating voltage reference. When the control unit receives a measured operating voltage reference, the control unit determines an updated age of the region different from the current age based on the measured operating voltage reference. The control unit updates the age counter with the corresponding age, which is younger than the previous age in some cases due to the region not experiencing predicted stress and aging. The control unit is capable of determining a voltage adjustment for the operating voltage reference based on an age indicated by the age counter.

3. 发明授权

US09372499B2 Low insertion delay clock doubler and integrated circuit clock distribution system using same 有权
标题翻译：低插入延迟时钟倍频器和集成电路时钟分配系统使用相同
公开(公告)号：US09372499B2
公开(公告)日：2016-06-21
申请号：US14159967
申请日：2014-01-21
申请人： Advanced Micro Devices, Inc.
发明人： Sriram Sambamurthy , Arun Sundaresan Iyer , Alok Baluni , Aaron Grenat
IPC分类号： H03B19/00 , G06F1/04 , H03K19/20 , H03K5/00 , H03K19/00
CPC分类号： G06F1/04 , G06F1/10 , H03K5/00006 , H03K19/0013 , H03K19/20
摘要： A clock doubler includes a first NAND gate having a first input for receiving a clock input signal and a second input, a second NAND gate having a first input and a second input for receiving a complement of the clock input signal, an output NAND gate having a first and second inputs coupled to outputs of the first and second NAND gates, respectively, and an output for providing a clock output signal, an inverter chain having an input for receiving the clock input signal and responsive to first and second control signals to selectively provide a first true output to the first input of the second NAND gate, and a second complementary output to the second input of the first NAND gate, and a control signal generation circuit providing the first and second control signals in response to the outputs of the first and second NAND gates.
摘要翻译：时钟倍频器包括具有用于接收时钟输入信号和第二输入的第一输入的第一NAND门，具有第一输入和第二输入的第二NAND门，用于接收时钟输入信号的补码;输出NAND门，具有分别耦合到第一和非门的输出的第一和第二输入以及用于提供时钟输出信号的输出，具有用于接收时钟输入信号的输入的反相器链，并响应第一和第二控制信号选择性地向第二NAND门的第一输入提供第一真实输出，以及向第一NAND门的第二输入提供第二互补输出;以及控制信号生成电路，响应于第一NAND门的输出而提供第一和第二控制信号第一和第二NAND门。

4. 发明授权

US12130692B2 Low power state selection based on idle duration history 有权
公开(公告)号：US12130692B2
公开(公告)日：2024-10-29
申请号：US17993562
申请日：2022-11-23
申请人： ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
发明人： Karthik Rao , Indrani Paul , Donny Yi , Oleksandr Khodorkovsky , Leonardo De Paula Rosa Piga , Wonje Choi , Dana G. Lewis , Sriram Sambamurthy
IPC分类号： G06F1/32 , G06F1/3287
CPC分类号： G06F1/3287
摘要： An apparatus includes a processor, a sleep state duration prediction module, and a system management unit. The sleep state duration prediction module is configured to predict a sleep state duration for component of the processing device. The system management unit is to transition the component into a sleep state selected from a plurality of sleep states based on a comparison of the predicted sleep state duration to at least one duration threshold. Each sleep state of the plurality of sleep states is a lower power state than a previous sleep state of the plurality of sleep states.

5. 发明公开

US20230350480A1 PLATFORM POWER MANAGER FOR RACK LEVEL POWER AND THERMAL CONSTRAINTS 审中-公开
公开(公告)号：US20230350480A1
公开(公告)日：2023-11-02
申请号：US18213596
申请日：2023-06-23
申请人： Advanced Micro Devices, Inc. , ATI Technologies ULC
发明人： Indrani Paul , Sriram Sambamurthy , Larry David Hewitt , Kevin M. Lepak , Samuel D. Naffziger , Adam Neil Calder Clark , Aaron Joseph Grenat , Steven Frederick Liepe , Sandhya Shyamasundar , Wonje Choi , Dana Glenn Lewis , Leonardo de Paula Rosa Piga
IPC分类号： G06F1/3225 , G06F1/3234
CPC分类号： G06F1/3225 , G06F1/3275 , G06F1/3203
摘要： Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.

6. 发明申请

US20210349517A1 PLATFORM POWER MANAGER FOR RACK LEVEL POWER AND THERMAL CONSTRAINTS 有权
公开(公告)号：US20210349517A1
公开(公告)日：2021-11-11
申请号：US17381664
申请日：2021-07-21
申请人： Advanced Micro Devices, Inc. , ATI Technologies ULC
发明人： Indrani Paul , Sriram Sambamurthy , Larry David Hewitt , Kevin M. Lepak , Samuel D. Naffziger , Adam Neil Calder Clark , Aaron Joseph Grenat , Steven Frederick Liepe , Sandhya Shyamasundar , Wonje Choi , Dana Glenn Lewis , Leonardo de Paula Rosa Piga
IPC分类号： G06F1/3225 , G06F1/3234
摘要： Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.

7. 发明申请

US20200379544A1 PLATFORM POWER MANAGER FOR RACK LEVEL POWER AND THERMAL CONSTRAINTS 审中-公开
公开(公告)号：US20200379544A1
公开(公告)日：2020-12-03
申请号：US16428312
申请日：2019-05-31
申请人： Advanced Micro Devices, Inc. , ATI Technologies ULC
发明人： Indrani Paul , Sriram Sambamurthy , Larry David Hewitt , Kevin M. Lepak , Samuel D. Naffziger , Adam Neil Calder Clark , Aaron Joseph Grenat , Steven Frederick Liepe , Sandhya Shyamasundar , Wonje Choi , Dana Glenn Lewis , Leonardo de Paula Rosa Piga
IPC分类号： G06F1/3225 , G06F1/3234
摘要： Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.

8. 发明公开

US20240235376A1 VOLTAGE REGULATOR WITH ACTIVE SHUNT 审中-公开
公开(公告)号：US20240235376A1
公开(公告)日：2024-07-11
申请号：US18478485
申请日：2023-09-29
申请人： Advanced Micro Devices, Inc. , ATI Technologies ULC
发明人： David King Wai Li , Amanullah Samit , Indrani Paul , Meeta Surendramohan Srivastav , Sriram Sambamurthy
IPC分类号： H02M1/32 , H02M3/02
CPC分类号： H02M1/32 , H02M3/02
摘要： The disclosed voltage regulator circuit includes a capacitor bank configured for a first voltage step corresponding to a voltage undershoot, and a shunt circuit configured for a second voltage step exceeding the first voltage step. Various other methods, systems, and computer-readable media are also disclosed.

9. 发明授权

US11714442B2 Controlling electrical power consumption for elements in an electronic device based on a platform electrical power limit 有权
公开(公告)号：US11714442B2
公开(公告)日：2023-08-01
申请号：US17560823
申请日：2021-12-23
申请人： Advanced Micro Devices, Inc. , ATI Technologies ULC
发明人： Meeta Surendramohan Srivastav , Ashwini Chandrashekhara Holla , Alex Sabino Duenas , Xinzhe Li , Michael John Austin , Indrani Paul , Sriram Sambamurthy
IPC分类号： G06F1/28 , G05F1/66
CPC分类号： G05F1/66 , G06F1/28
摘要： An electronic device includes an accelerated processing unit (APU) and multiple elements. The APU performs operations for a platform boost and throttle (PBT) controller. For the operations, the APU receives a platform electrical power limit, the platform electrical power limit being a limit on a total electrical power allowed to be consumed by a group of the elements at a given time. The APU then determines a present platform electrical power consumption. The APU next adjusts one or more operating parameters for specified elements from among the group of elements to control electrical power consumption by the specified elements based on a relationship between the present platform electrical power consumption and the platform electrical power limit.

10. 发明授权

US11703930B2 Platform power manager for rack level power and thermal constraints 有权
公开(公告)号：US11703930B2
公开(公告)日：2023-07-18
申请号：US17381664
申请日：2021-07-21
申请人： Advanced Micro Devices, Inc. , ATI Technologies ULC
发明人： Indrani Paul , Sriram Sambamurthy , Larry David Hewitt , Kevin M. Lepak , Samuel D. Naffziger , Adam Neil Calder Clark , Aaron Joseph Grenat , Steven Frederick Liepe , Sandhya Shyamasundar , Wonje Choi , Dana Glenn Lewis , Leonardo de Paula Rosa Piga
IPC分类号： G06F1/00 , G06F1/3225 , G06F1/3234 , G06F1/3203 , G06F1/26
CPC分类号： G06F1/3225 , G06F1/3275 , G06F1/26 , G06F1/3203
摘要： Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.

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