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1. 发明授权

US10970081B2 Stream processor with decoupled crossbar for cross lane operations 有权
公开(公告)号：US10970081B2
公开(公告)日：2021-04-06
申请号：US15637629
申请日：2017-06-29
申请人： Advanced Micro Devices, Inc.
发明人： Jiasheng Chen , Bin He , Mohammad Reza Hakami , Timothy Lottes , Justin David Smith , Michael J. Mantor , Derek Carson
IPC分类号： G06F9/30 , G06F9/38 , G06F9/52
摘要： Systems, apparatuses, and methods for implementing a decoupled crossbar for a stream processor are disclosed. In one embodiment, a system includes at least a multi-lane execution pipeline, a vector register file, and a crossbar. The system is configured to determine if a given instruction in an instruction stream requires a permutation on data operands retrieved from the vector register file. The system conveys the data operands to the multi-lane execution pipeline on a first path which includes the crossbar responsive to determining the given instruction requires a permutation on the data operands. The crossbar then performs the necessary permutation to route the data operands to the proper processing lanes. Otherwise, the system conveys the data operands to the multi-lane execution pipeline on a second path which bypasses the crossbar responsive to determining the given instruction does not require a permutation on the input operands.

2. 发明申请

US20210090208A1 REDUNDANCY METHOD AND APPARATUS FOR SHADER COLUMN REPAIR 有权
公开(公告)号：US20210090208A1
公开(公告)日：2021-03-25
申请号：US17113827
申请日：2020-12-07
申请人： Advanced Micro Devices, Inc.
发明人： Michael J. Mantor , Jeffrey T. Brady , Angel E. Socarras
IPC分类号： G06T1/20 , G06T1/60 , G09G5/36
摘要： Methods and systems are described. A system includes a redundant shader pipe array that performs rendering calculations on data provided thereto and a shader pipe array that includes a plurality of shader pipes, each of which performs rendering calculations on data provided thereto. The system also includes a circuit that identifies a defective shader pipe of the plurality of shader pipes in the shader pipe array. In response to identifying the defective shader pipe, the circuit generates a signal. The system also includes a redundant shader switch. The redundant shader switch receives the generated signal, and, in response to receiving the generated signal, transfers the data for the defective shader pipe to the redundant shader pipe array.

3. 发明授权

US10817302B2 Processor support for bypassing vector source operands 有权
公开(公告)号：US10817302B2
公开(公告)日：2020-10-27
申请号：US15644045
申请日：2017-07-07
申请人： Advanced Micro Devices, Inc.
发明人： Jiasheng Chen , Bin He , Mark M. Leather , Michael J. Mantor , Yunxiao Zou
IPC分类号： G06F9/38 , G06F9/30 , G06F12/0891 , G06F12/0855 , G06F12/0804 , G06F12/121 , G06F12/0875
摘要： Systems, apparatuses, and methods for implementing a high bandwidth, low power vector register file for use by a parallel processor are disclosed. In one embodiment, a system includes at least a parallel processing unit with a plurality of processing pipeline. The parallel processing unit includes a vector arithmetic logic unit and a high bandwidth, low power, vector register file. The vector register file includes multi-bank high density random-access memories (RAMs) to satisfy register bandwidth requirements. The parallel processing unit also includes an instruction request queue and an instruction operand buffer to provide enough local bandwidth for VALU instructions and vector I/O instructions. Also, the parallel processing unit is configured to leverage the RAM's output flops as a last level cache to reduce duplicate operand requests between multiple instructions. The parallel processing unit includes a vector destination cache to provide additional R/W bandwidth for the vector register file.

4. 发明授权

US10180789B2 Software control of state sets 有权
公开(公告)号：US10180789B2
公开(公告)日：2019-01-15
申请号：US15417011
申请日：2017-01-26
申请人： Advanced Micro Devices, Inc.
发明人： Rex Eldon McCrary , Michael J. Mantor , Alexander Fuad Ashkar , Harry J. Wise
IPC分类号： G06F12/00 , G06F3/06 , G06F9/48 , G06F9/50
摘要： Systems, apparatuses, and methods for implementing software control of state sets are disclosed. In one embodiment, a processor includes at least an execution unit and a plurality of state registers. The processor is configured to detect a command to allocate a first state set for storing a first state, wherein the command is generated by software, and wherein the first state specifies values for the plurality of state registers. The command is executed on the execution unit while the processor is in a second state, wherein the second state is different from the first state. The first state set of the processor is allocated with the first state responsive to executing the command on the execution unit. The processor is configured to allocate the first state set for the first state prior to the processor entering the first state.

5. 发明申请

US20190004814A1 STREAM PROCESSOR WITH DECOUPLED CROSSBAR FOR CROSS LANE OPERATIONS 审中-公开
公开(公告)号：US20190004814A1
公开(公告)日：2019-01-03
申请号：US15637629
申请日：2017-06-29
申请人： Advanced Micro Devices, Inc.
发明人： Jiasheng Chen , Bin He , Mohammad Reza Hakami , Timothy Lottes , Justin David Smith , Michael J. Mantor , Derek Carson
IPC分类号： G06F9/38 , G06F9/52 , G06F9/30
摘要： Systems, apparatuses, and methods for implementing a decoupled crossbar for a stream processor are disclosed. In one embodiment, a system includes at least a multi-lane execution pipeline, a vector register file, and a crossbar. The system is configured to determine if a given instruction in an instruction stream requires a permutation on data operands retrieved from the vector register file. The system conveys the data operands to the multi-lane execution pipeline on a first path which includes the crossbar responsive to determining the given instruction requires a permutation on the data operands. The crossbar then performs the necessary permutation to route the data operands to the proper processing lanes. Otherwise, the system conveys the data operands to the multi-lane execution pipeline on a second path which bypasses the crossbar responsive to determining the given instruction does not require a permutation on the input operands.

6. 发明申请

US20230097097A1 GRAPHICS PRIMITIVES AND POSITIONS THROUGH MEMORY BUFFERS 有权
公开(公告)号：US20230097097A1
公开(公告)日：2023-03-30
申请号：US17489105
申请日：2021-09-29
申请人： Advanced Micro Devices, Inc.
发明人： Todd Martin , Tad Robert Litwiller , Nishank Pathak , Randy Wayne Ramsey , Michael J. Mantor , Christopher J. Brennan , Mark M. Leather , Ryan James Cash
IPC分类号： G06T15/80 , G06T1/20 , G06T1/60 , G06T15/00
摘要： Systems, apparatuses, and methods for preemptively reserving buffer space for primitives and positions in a graphics pipeline are disclosed. A system includes a graphics pipeline frontend with any number of geometry engines coupled to corresponding shader engines. Each geometry engine launches shader wavefronts to execute on a corresponding shader engine. The geometry engine preemptively reserves buffer space for each wavefront prior to the wavefront being launched on the shader engine. When the shader engine executes a wavefront, the shader engine exports primitive and position data to the reserved buffer space. Multiple scan converters will consume the primitive and position data, with each scan converter consuming primitive and position data based on the screen coverage of the scan converter. After consuming the primitive and position data, the scan converters mark the buffer space as freed so that the geometry engine can then allocate the freed buffer space to subsequent shader wavefronts.

7. 发明申请

US20220343456A1 REDUNDANCY METHOD AND APPARATUS FOR SHADER COLUMN REPAIR 有权
公开(公告)号：US20220343456A1
公开(公告)日：2022-10-27
申请号：US17862096
申请日：2022-07-11
申请人： Advanced Micro Devices, Inc.
发明人： Michael J. Mantor , Jeffrey T. Brady , Angel E. Socarras
IPC分类号： G06T1/20 , G06T1/60 , G09G5/36
摘要： Methods and systems are described. A system includes a redundant shader pipe array that performs rendering calculations on data provided thereto and a shader pipe array that includes a plurality of shader pipes, each of which performs rendering calculations on data provided thereto. The system also includes a circuit that identifies a defective shader pipe of the plurality of shader pipes in the shader pipe array. In response to identifying the defective shader pipe, the circuit generates a signal. The system also includes a redundant shader switch. The redundant shader switch receives the generated signal, and, in response to receiving the generated signal, transfers the data for the defective shader pipe to the redundant shader pipe array.

8. 发明授权

US10929944B2 Low power and low latency GPU coprocessor for persistent computing 有权
公开(公告)号：US10929944B2
公开(公告)日：2021-02-23
申请号：US15360057
申请日：2016-11-23
申请人： Advanced Micro Devices, Inc.
发明人： Jiasheng Chen , Timour Paltashev , Alexander Lyashevsky , Carl Kittredge Wakeland , Michael J. Mantor
IPC分类号： G06T1/20 , G06F9/54 , G06F9/38 , G06T1/60
摘要： Systems, apparatuses, and methods for implementing a graphics processing unit (GPU) coprocessor are disclosed. The GPU coprocessor includes a SIMD unit with the ability to self-schedule sub-wave procedures based on input data flow events. A host processor sends messages targeting the GPU coprocessor to a queue. In response to detecting a first message in the queue, the GPU coprocessor schedules a first sub-task for execution. The GPU coprocessor includes an inter-lane crossbar and intra-lane biased indexing mechanism for a vector general purpose register (VGPR) file. The VGPR file is split into two files. The first VGPR file is a larger register file with one read port and one write port. The second VGPR file is a smaller register file with multiple read ports and one write port. The second VGPR introduces the ability to co-issue more than one instruction per clock cycle.

9. 发明申请

US20180144435A1 LOW POWER AND LOW LATENCY GPU COPROCESSOR FOR PERSISTENT COMPUTING 审中-公开
公开(公告)号：US20180144435A1
公开(公告)日：2018-05-24
申请号：US15360057
申请日：2016-11-23
申请人： Advanced Micro Devices, Inc.
发明人： Jiasheng Chen , Timour Paltashev , Alexander Lyashevsky , Carl Kittredge Wakeland , Michael J. Mantor
IPC分类号： G06T1/20 , G06T1/60
CPC分类号： G06T1/20 , G06F9/3887 , G06F9/542 , G06F2009/3883 , G06F2209/548 , G06T1/60
摘要： Systems, apparatuses, and methods for implementing a graphics processing unit (GPU) coprocessor are disclosed. The GPU coprocessor includes a SIMD unit with the ability to self-schedule sub-wave procedures based on input data flow events. A host processor sends messages targeting the GPU coprocessor to a queue. In response to detecting a first message in the queue, the GPU coprocessor schedules a first sub-task for execution. The GPU coprocessor includes an inter-lane crossbar and intra-lane biased indexing mechanism for a vector general purpose register (VGPR) file. The VGPR file is split into two files. The first VGPR file is a larger register file with one read port and one write port. The second VGPR file is a smaller register file with multiple read ports and one write port. The second VGPR introduces the ability to co-issue more than one instruction per clock cycle.

10. 发明申请

US20150332427A1 REDUNDANCY METHOD AND APPARATUS FOR SHADER COLUMN REPAIR 审中-公开
标题翻译：冗余方法和设备用于阴影柱修复
公开(公告)号：US20150332427A1
公开(公告)日：2015-11-19
申请号：US14808113
申请日：2015-07-24
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Michael J. Mantor , Jeffrey T. Brady , Angel E. Socarras
IPC分类号： G06T1/20 , G06T1/60
CPC分类号： G06T1/20 , G06T1/60 , G09G5/363 , G09G2360/06
摘要： Methods, systems and non-transitory computer readable media are described. A system includes a shader pipe array, a redundant shader pipe array, a sequencer and a redundant shader switch. The shader pipe array includes multiple shader pipes, each of which perform rendering calculations on data provided thereto. The redundant shader pipe array also performs rendering calculations on data provided thereto. The sequencer identifies at least one defective shader pipe in the shader pipe array, and, in response, generates a signal. The redundant shader switch receives the generated signal, and, in response, transfers the data destined for each shader pipe identified as being defective independently to the redundant shader pipe array.
摘要翻译：描述了方法，系统和非暂时性计算机可读介质。系统包括着色器管道阵列，冗余着色器管道阵列，定序器和冗余着色器开关。着色器管道阵列包括多个着色器管道，每个管道对其提供的数据执行渲染计算。冗余着色器管道阵列还对提供给它的数据执行渲染计算。定序器在着色器管道阵列中识别至少一个有缺陷的着色器管道，并作为响应生成信号。冗余着色器开关接收所生成的信号，并作为响应，将指定为每个着色器管道的数据独立地传输到冗余着色器管道阵列。

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