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1. 发明申请

US20110202789A1 PROCESSOR-MEMORY UNIT FOR USE IN SYSTEM-IN-PACKAGE AND SYSTEM-IN-MODULE DEVICES 有权
标题翻译：用于系统级封装和系统模块内设备的处理器存储单元
公开(公告)号：US20110202789A1
公开(公告)日：2011-08-18
申请号：US13093720
申请日：2011-04-25
申请人： Adrian E. Ong , Naresh Baliga
发明人： Adrian E. Ong , Naresh Baliga
IPC分类号： G06F11/16 , G06F11/20
CPC分类号： G11C29/56 , G11C5/04 , G11C2029/5602
摘要： An apparatus and method for a processor-memory unit for use in system-in-package (SiP) and system-in-package (SiP) integrated circuit devices. The apparatus includes a processing module, a memory module and a programmable system module. The programmable system module is configured to function as an interface between the memory module and the processing module, or as an interface between the memory module and a testing device. The invention facilitates integration and testing of processor-memory units including functional components having different communication protocols.
摘要翻译：一种用于在系统级封装（SiP）和系统级封装（SiP））集成电路器件中使用的处理器存储器单元的装置和方法。该装置包括处理模块，存储模块和可编程系统模块。可编程系统模块被配置为用作存储器模块和处理模块之间的接口，或者作为存储器模块和测试设备之间的接口。本发明便于包括具有不同通信协议的功能组件的处理器存储器单元的集成和测试。

2. 发明授权

US07673193B1 Processor-memory unit for use in system-in-package and system-in-module devices 有权
标题翻译：处理器内存单元，用于系统级封装和系统级模块设备
公开(公告)号：US07673193B1
公开(公告)日：2010-03-02
申请号：US11208099
申请日：2005-08-18
申请人： Adrian E. Ong , Naresh Baliga
发明人： Adrian E. Ong , Naresh Baliga
IPC分类号： G11C29/00
CPC分类号： G11C29/56 , G11C5/04 , G11C2029/5602
摘要： An apparatus and method for a processor-memory unit for use in system-in-package (SiP) and system-in-package (SiP) integrated circuit devices. The apparatus includes a processing module, a memory module and a programmable system module. The programmable system module is configured to function as an interface between the memory module and the processing module, or as an interface between the memory module and a testing device. The invention facilitates integration and testing of processor-memory units including functional components having different communication protocols.
摘要翻译：一种用于在系统级封装（SiP）和系统级封装（SiP））集成电路器件中使用的处理器存储器单元的装置和方法。该装置包括处理模块，存储模块和可编程系统模块。可编程系统模块被配置为用作存储器模块和处理模块之间的接口，或者作为存储器模块和测试设备之间的接口。本发明便于包括具有不同通信协议的功能组件的处理器存储器单元的集成和测试。

3. 发明授权

US07466160B2 Shared memory bus architecture for system with processor and memory units 有权
标题翻译：具有处理器和存储单元的系统的共享内存总线架构
公开(公告)号：US07466160B2
公开(公告)日：2008-12-16
申请号：US11472016
申请日：2006-06-20
申请人： Adrian E. Ong , Naresh Baliga , Chiate Lin
发明人： Adrian E. Ong , Naresh Baliga , Chiate Lin
IPC分类号： G01R31/28 , G11C29/00 , G11C7/00
CPC分类号： G01R31/31722 , G01R31/31723 , H01L2224/05554 , H01L2224/48091 , H01L2224/48137 , H01L2224/48139 , H01L2924/00014
摘要： A system is provided for testing a first integrated circuit associated with at least a second integrated circuit in a semiconductor device, wherein at least some external terminals for the semiconductor device are to be shared by the first and second integrated circuits, and wherein the first integrated circuit is designed for normal operation and a test mode. The system includes a plurality of multiplexer circuits. Each multiplexer circuit is operable to receive a respective signal from the second integrated circuit when the first integrated circuit is in normal operation. Each multiplexer circuit is further operable to receive a respective signal from either the second integrated circuit or an associated external terminal when the first integrated circuit is in test mode. An external terminal of the semiconductor device operable to receive a signal for causing the first integrated circuit to transition between normal operation and the test mode.
摘要翻译：提供了一种用于测试与半导体器件中的至少第二集成电路相关联的第一集成电路的系统，其中用于半导体器件的至少一些外部端子将被第一和第二集成电路共享，并且其中第一集成电路设计用于正常运行和测试模式。该系统包括多个多路复用器电路。当第一集成电路处于正常操作时，每个复用器电路可操作以接收来自第二集成电路的相应信号。当第一集成电路处于测试模式时，每个多路复用器电路还可操作以从第二集成电路或相关联的外部端子接收相应的信号。半导体器件的外部端子可操作以接收用于使第一集成电路在正常操作和测试模式之间转变的信号。

4. 发明授权

US08195992B2 Processor-memory unit for use in system-in-package and system-in-module devices 有权
标题翻译：处理器内存单元，用于系统级封装和系统级模块设备
公开(公告)号：US08195992B2
公开(公告)日：2012-06-05
申请号：US13093720
申请日：2011-04-25
申请人： Adrian E. Ong , Naresh Baliga
发明人： Adrian E. Ong , Naresh Baliga
IPC分类号： G11C29/00
CPC分类号： G11C29/56 , G11C5/04 , G11C2029/5602
摘要： An apparatus and method for a processor-memory unit for use in system-in-package (SiP) and system-in-package (SiP) integrated circuit devices. The apparatus includes a processing module, a memory module and a programmable system module. The programmable system module is configured to function as an interface between the memory module and the processing module, or as an interface between the memory module and a testing device. The invention facilitates integration and testing of processor-memory units including functional components having different communication protocols.
摘要翻译：一种用于在系统级封装（SiP）和系统级封装（SiP））集成电路器件中使用的处理器存储器单元的装置和方法。该装置包括处理模块，存储模块和可编程系统模块。可编程系统模块被配置为用作存储器模块和处理模块之间的接口，或者作为存储器模块和测试设备之间的接口。本发明便于包括具有不同通信协议的功能组件的处理器存储器单元的集成和测试。

5. 发明授权

US07945824B2 Processor-memory unit for use in system-in-package and system-in-module devices 有权
标题翻译：处理器内存单元，用于系统级封装和系统级模块设备
公开(公告)号：US07945824B2
公开(公告)日：2011-05-17
申请号：US12646540
申请日：2009-12-23
申请人： Adrian E. Ong , Naresh Baliga
发明人： Adrian E. Ong , Naresh Baliga
IPC分类号： G11C29/00
CPC分类号： G11C29/56 , G11C5/04 , G11C2029/5602
摘要： An apparatus and method for a processor-memory unit for use in system-in-package (SiP) and system-in-package (SiP) integrated circuit devices. The apparatus includes a processing module, a memory module and a programmable system module. The programmable system module is configured to function as an interface between the memory module and the processing module, or as an interface between the memory module and a testing device. The invention facilitates integration and testing of processor-memory units including functional components having different communication protocols.
摘要翻译：一种用于在系统级封装（SiP）和系统级封装（SiP））集成电路器件中使用的处理器存储器单元的装置和方法。该装置包括处理模块，存储模块和可编程系统模块。可编程系统模块被配置为用作存储器模块和处理模块之间的接口，或者作为存储器模块和测试设备之间的接口。本发明便于包括具有不同通信协议的功能组件的处理器存储器单元的集成和测试。

6. 发明申请

US20100100661A1 PROCESSOR-MEMORY UNIT FOR USE IN SYSTEM-IN-PACKAGE AND SYSTEM-IN-MODULE DEVICES 有权
标题翻译：用于系统级封装和系统模块内设备的处理器存储单元
公开(公告)号：US20100100661A1
公开(公告)日：2010-04-22
申请号：US12646540
申请日：2009-12-23
申请人： Adrian E. Ong , Naresh Baliga
发明人： Adrian E. Ong , Naresh Baliga
IPC分类号： G06F12/06
CPC分类号： G11C29/56 , G11C5/04 , G11C2029/5602
摘要： An apparatus and method for a processor-memory unit for use in system-in-package (SiP) and system-in-package (SiP) integrated circuit devices. The apparatus includes a processing module, a memory module and a programmable system module. The programmable system module is configured to function as an interface between the memory module and the processing module, or as an interface between the memory module and a testing device. The invention facilitates integration and testing of processor-memory units including functional components having different communication protocols.
摘要翻译：一种用于在系统级封装（SiP）和系统级封装（SiP））集成电路器件中使用的处理器存储器单元的装置和方法。该装置包括处理模块，存储模块和可编程系统模块。可编程系统模块被配置为用作存储器模块和处理模块之间的接口，或者作为存储器模块和测试设备之间的接口。本发明便于包括具有不同通信协议的功能组件的处理器存储器单元的集成和测试。

7. 发明申请

US20070013402A1 Shared memory bus architecture for system with processor and memory units 有权
标题翻译：具有处理器和存储单元的系统的共享内存总线架构
公开(公告)号：US20070013402A1
公开(公告)日：2007-01-18
申请号：US11472016
申请日：2006-06-20
申请人： Adrian Ong , Naresh Baliga , Chiate Lin
发明人： Adrian Ong , Naresh Baliga , Chiate Lin
IPC分类号： G01R31/26
CPC分类号： G01R31/31722 , G01R31/31723 , H01L2224/05554 , H01L2224/48091 , H01L2224/48137 , H01L2224/48139 , H01L2924/00014
摘要： A system is provided for testing a first integrated circuit associated with at least a second integrated circuit in a semiconductor device, wherein at least some external terminals for the semiconductor device are to be shared by the first and second integrated circuits, and wherein the first integrated circuit is designed for normal operation and a test mode. The system includes a plurality of multiplexer circuits. Each multiplexer circuit is operable to receive a respective signal from the second integrated circuit when the first integrated circuit is in normal operation. Each multiplexer circuit is further operable to receive a respective signal from either the second integrated circuit or an associated external terminal when the first integrated circuit is in test mode. An external terminal of the semiconductor device operable to receive a signal for causing the first integrated circuit to transition between normal operation and the test mode
摘要翻译：提供了一种用于测试与半导体器件中的至少第二集成电路相关联的第一集成电路的系统，其中用于半导体器件的至少一些外部端子将由第一和第二集成电路共享，并且其中第一集成电路设计用于正常运行和测试模式。该系统包括多个多路复用器电路。当第一集成电路处于正常操作时，每个复用器电路可操作以接收来自第二集成电路的相应信号。当第一集成电路处于测试模式时，每个多路复用器电路还可操作以从第二集成电路或相关联的外部端子接收相应的信号。半导体器件的外部端子可操作以接收用于使第一集成电路在正常操作和测试模式之间转变的信号

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