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1. 发明授权

US09336868B1 Common plate switching reduction in resistive switching memory devices 有权
标题翻译：电阻式开关存储器件中普通板开关减少
公开(公告)号：US09336868B1
公开(公告)日：2016-05-10
申请号：US13909983
申请日：2013-06-04
申请人： Adesto Technologies Corporation
发明人： Shane Charles Hollmer , Derric Lewis , John Dinh , Nad Edward Gilbert
IPC分类号： G11C13/00
CPC分类号： G11C13/0007 , G11C13/0011 , G11C13/003 , G11C13/0064 , G11C13/0069 , G11C13/0097 , G11C2013/0073 , G11C2213/79 , G11C2213/82
摘要： Structures and operations of a resistive switching memory device are described herein. In one embodiment, a resistive switching memory device can include: a plurality of resistive memory cells, each configured to be programmed to a low resistance state by application of a first voltage in a forward bias direction, and erased to a high resistance state by application of a second voltage in a reverse bias direction; a plurality of common plates, each being connected to a subset of the resistive memory cells; a command detector configured to detect a write command to be executed as a first and second write operations; and a write controller configured to perform the first write operation on each resistive memory cell in a selected subset, and to perform the second write operation on at least one of the resistive memory cells in the selected subset based on the detected write command.
摘要翻译：这里描述了电阻式开关存储器件的结构和操作。在一个实施例中，电阻式开关存储器件可以包括：多个电阻存储器单元，每个电阻存储器单元经配置以通过在正向偏压方向施加第一电压而被编程为低电阻状态，并通过应用擦除为高电阻状态反向偏置方向上的第二电压; 多个公共板，各自连接到电阻存储器单元的子集; 命令检测器，被配置为检测要作为第一和第二写入操作执行的写入命令; 以及写入控制器，被配置为对所选择的子集中的每个电阻式存储器单元执行第一写入操作，并且基于检测到的写入命令对所选择的子集中的至少一个电阻存储器单元执行第二写入操作。

2. 发明授权

US10409505B2 Ultra-deep power down mode control in a memory device 有权
公开(公告)号：US10409505B2
公开(公告)日：2019-09-10
申请号：US15576941
申请日：2016-04-13
申请人： Adesto Technologies Corporation
发明人： Derric Lewis , John Dinh , Gideon Intrater , Nathan Gonzales
IPC分类号： G06F3/06 , G06F1/24 , G06F1/3234 , G06F1/3287 , G06F1/3296 , G06F13/42 , G11C5/14 , G11C11/417
摘要： A method of controlling an ultra-deep power down (UDPD) mode in a memory device, can include: receiving a write command from a host via an interface; beginning a write operation on the memory device to execute the write command; reading an auto-UDPD (AUDPD) configuration bit from a status register; completing the write operation on the memory device; automatically entering the UDPD mode upon completion of the write operation in response to the AUDPD configuration bit being set; and entering a standby mode upon completion of the write operation in response to the AUDPD configuration bit being cleared.

3. 发明授权

US09922684B2 Memory device ultra-deep power-down mode exit control 有权
公开(公告)号：US09922684B2
公开(公告)日：2018-03-20
申请号：US15409270
申请日：2017-01-18
申请人： Adesto Technologies Corporation
发明人： Bard M. Pedersen , Derric Lewis , John Dinh , Gideon Intrater , Nathan Gonzales
IPC分类号： G11C5/14 , G11C11/4074
CPC分类号： G11C5/148 , G11C5/14 , G11C5/147 , G11C11/4074
摘要： A memory device operable in an ultra-deep power-down mode can include: a command user interface; a voltage regulator having an output that provides a supply voltage for a plurality of components of the memory device, where the plurality of components comprises the command user interface; a wake-up circuit that remains powered on even when the memory device is in the ultra-deep power-down mode; the memory device being operable to enter the ultra-deep power-down mode in response to receiving a first predetermined command that causes the output of the voltage regulator to be disabled to completely power down the plurality of components during the ultra-deep power-down mode; and the memory device being operable to exit the ultra-deep power-down mode in response to receiving one of a hardware reset command sequence, a reset pin assertion, a power supply cycling, and a second predetermined command.

4. 发明授权

US09812200B2 Concurrent read and write operations in a serial flash device 有权
公开(公告)号：US09812200B2
公开(公告)日：2017-11-07
申请号：US14719814
申请日：2015-05-22
申请人： Adesto Technologies Corporation
发明人： Gideon Intrater , Bard Pedersen , Shane Hollmer , Derric Lewis , Stephen Trinh
IPC分类号： G11C13/00 , G06F13/16 , G11C16/32 , G11C29/02 , G11C7/22
CPC分类号： G11C13/0069 , G06F13/1668 , G11C7/227 , G11C13/0011 , G11C13/0023 , G11C13/004 , G11C13/0061 , G11C16/32 , G11C29/021 , G11C29/028 , G11C2213/71 , G11C2216/20
摘要： A method of controlling an NVM device can include: (i) receiving, by an interface, a write command from a host; (ii) beginning execution of a write operation on a first array plane of a memory array in response to the write command, where the memory array includes a plurality of NVM cells arranged in a plurality of array planes; (iii) receiving, by the interface, a read command from the host; (iv) suspending the write operation in response to detection of the read command during execution of the write operation; (v) beginning execution of a read operation on a second array plane in response to the read command; and (vi) resuming the write operation after the read operation has at least partially been executed.

5. 发明申请

US20170236561A1 MEMORY DEVICE ULTRA-DEEP POWER-DOWN MODE EXIT CONTROL 有权
公开(公告)号：US20170236561A1
公开(公告)日：2017-08-17
申请号：US15409270
申请日：2017-01-18
申请人： Adesto Technologies Corporation
发明人： Bard M. Pedersen , Derric Lewis , John Dinh , Gideon Intrater , Nathan Gonzales
IPC分类号： G11C5/14
CPC分类号： G11C5/148 , G11C5/14 , G11C5/147 , G11C11/4074
摘要： A memory device operable in an ultra-deep power-down mode can include: a command user interface; a voltage regulator having an output that provides a supply voltage for a plurality of components of the memory device, where the plurality of components comprises the command user interface; a wake-up circuit that remains powered on even when the memory device is in the ultra-deep power-down mode; the memory device being operable to enter the ultra-deep power-down mode in response to receiving a first predetermined command that causes the output of the voltage regulator to be disabled to completely power down the plurality of components during the ultra-deep power-down mode; and the memory device being operable to exit the ultra-deep power-down mode in response to receiving one of a hardware reset command sequence, a reset pin assertion, a power supply cycling, and a second predetermined command.

6. 发明授权

US09007808B1 Safeguarding data through an SMT process 有权
标题翻译：通过SMT流程保护数据
公开(公告)号：US09007808B1
公开(公告)日：2015-04-14
申请号：US13628385
申请日：2012-09-27
申请人： Adesto Technologies Corporation
发明人： John Dinh , Derric Lewis , Venkatesh P. Gopinath , Deepak Kamalanathan , Shane C. Hollmer , Juan Pablo Saenz Echeverry
IPC分类号： G11C11/00 , G11C13/00 , G11C11/406 , G11C13/02
CPC分类号： G11C13/0011 , G11C11/406 , G11C11/40603 , G11C11/40626 , G11C13/0009 , G11C13/0033 , G11C13/004 , G11C13/0069 , G11C13/02 , G11C2013/0083
摘要： Structures and methods for recovering data in a semiconductor memory device are disclosed herein. In one embodiment, a method of recovering data in a semiconductor memory device, can include: (i) pre-conditioning a first memory cell on the semiconductor memory device by using a formation voltage to program a first data state in the first memory cell; (ii) storing a second data state in a second memory cell on the semiconductor memory device by maintaining the second memory cell in a virgin state; (iii) mounting the semiconductor memory device on a printed-circuit board (PCB) by using a high temperature process that increases a resistance of the first memory cell; and (iv) performing a recovery of the first data state by reducing the resistance of the first memory cell.
摘要翻译：本文公开了用于在半导体存储器件中恢复数据的结构和方法。在一个实施例中，一种在半导体存储器件中恢复数据的方法可以包括：（i）通过使用地层电压对第一存储器单元中的第一数据状态进行编程来预调节半导体存储器件上的第一存储单元; （ii）通过将第二存储单元维持在处女状态，将第二数据状态存储在半导体存储器件上的第二存储单元中; （iii）通过使用增加第一存储单元的电阻的高温处理将半导体存储器件安装在印刷电路板（PCB）上; 和（iv）通过减小第一存储单元的电阻来执行第一数据状态的恢复。

7. 发明授权

US10636480B2 Concurrent read and reconfigured write operations in a memory device 有权
公开(公告)号：US10636480B2
公开(公告)日：2020-04-28
申请号：US15568713
申请日：2016-05-02
申请人： Adesto Technologies Corporation
发明人： Gideon Intrater , Bard Pedersen , Shane Hollmer , Derric Lewis , Stephen Trinh
IPC分类号： G11C11/419 , G11C8/12 , G11C7/22 , G11C13/00 , G11C16/10 , G11C16/26 , G11C16/34 , G11C29/02 , G11C5/14
CPC分类号： G11C11/419 , G11C7/22 , G11C8/12 , G11C13/004 , G11C13/0011 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C16/10 , G11C16/26 , G11C16/3459 , G11C29/021 , G11C29/028 , G11C5/141 , G11C2207/2209 , G11C2211/5623 , G11C2216/22
摘要： A method of controlling a memory device can include: receiving, by an interface, a write command from a host; beginning execution of a write operation on a first array plane of a memory array in response to the write command, where the memory array includes a plurality of memory cells arranged in a plurality of array planes; receiving, by the interface, a read command from the host; reconfiguring the write operation in response to detection of the read command during execution of the write operation; beginning execution of a read operation on a second array plane in response to the read command; and restoring the configuration of the write operation after the read operation has at least partially been executed.

8. 发明申请

US20180166130A1 CONCURRENT READ AND RECONFIGURED WRITE OPERATIONS IN A MEMORY DEVICE 审中-公开
公开(公告)号：US20180166130A1
公开(公告)日：2018-06-14
申请号：US15568713
申请日：2016-05-02
申请人： Adesto Technologies Corporation
发明人： Gideon Intrater , Bard Pedersen , Shane Hollmer , Derric Lewis , Stephen Trinh
IPC分类号： G11C11/419 , G11C13/00 , G11C16/10 , G11C16/26 , G11C16/34 , G11C29/02 , G11C7/22 , G11C8/12
CPC分类号： G11C11/419 , G11C5/141 , G11C7/22 , G11C8/12 , G11C13/0011 , G11C13/004 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C16/10 , G11C16/26 , G11C16/3459 , G11C29/021 , G11C29/028 , G11C2207/2209 , G11C2211/5623 , G11C2216/22
摘要： A method of controlling a memory device can include: receiving, by an interface, a write command from a host; beginning execution of a write operation on a first array plane of a memory array in response to the write command, where the memory array includes a plurality of memory cells arranged in a plurality of array planes; receiving, by the interface, a read command from the host; reconfiguring the write operation in response to detection of the read command during execution of the write operation; beginning execution of a read operation on a second array plane in response to the read command; and restoring the configuration of the write operation after the read operation has at least partially been executed.

9. 发明授权

US09368206B1 Capacitor arrangements using a resistive switching memory cell structure 有权
标题翻译：使用电阻式开关存储单元结构的电容器布置
公开(公告)号：US09368206B1
公开(公告)日：2016-06-14
申请号：US14325119
申请日：2014-07-07
申请人： Adesto Technologies Corporation
发明人： John Dinh , Ming Sang Kwan , Venkatesh P. Gopinath , Derric Lewis , Shane Hollmer , John R. Jameson , Michael Van Buskirk
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C11/24 , G11C11/5614 , G11C13/0011 , G11C13/003 , G11C13/0033 , G11C13/004 , G11C13/0097 , G11C2213/76 , G11C2213/78
摘要： In one embodiment, a capacitive circuit can include: (i) a resistive storage element having a solid electrolyte, a first electrode coupled to a first side of the solid electrolyte, and a second electrode coupled to a second side of the solid electrolyte; (ii) the resistive storage element being configured to be programmed to a low resistance state by application of a program voltage in a forward bias direction to form a conductive path between the first and second electrodes, and being configured to be erased to a high resistance state by application of an erase voltage in a reverse bias direction to substantially dissolve the conductive path; and (iii) a first capacitor having the first electrode coupled to a first side of a first oxide layer, and a third electrode coupled to a second side of the first oxide layer.
摘要翻译：在一个实施例中，电容电路可以包括：（i）具有固体电解质的电阻存储元件，耦合到固体电解质的第一侧的第一电极和耦合到固体电解质的第二侧的第二电极; （ii）电阻存储元件被配置为通过在正向偏置方向上施加编程电压而被编程为低电阻状态，以在第一和第二电极之间形成导电路径，并且被配置为被擦除为高电阻通过在反向偏置方向施加擦除电压以使导电路径基本上溶解; 和（iii）第一电容器，其具有耦合到第一氧化物层的第一侧的第一电极和耦合到第一氧化物层的第二侧的第三电极。

10. 发明授权

US11094375B2 Concurrent read and reconfigured write operations in a memory device 有权
公开(公告)号：US11094375B2
公开(公告)日：2021-08-17
申请号：US16807320
申请日：2020-03-03
申请人： Adesto Technologies Corporation
发明人： Gideon Intrater , Bard Pedersen , Shane Hollmer , Derric Lewis , Stephen Trinh
IPC分类号： G11C11/419 , G11C16/10 , G11C7/22 , G11C8/12 , G11C13/00 , G11C16/26 , G11C16/34 , G11C29/02 , G11C5/14
摘要： A method of controlling a memory device can include: receiving, by an interface, a write command from a host; beginning execution of a write operation on a first array plane of a memory array in response to the write command, where the memory array includes a plurality of memory cells arranged in a plurality of array planes; receiving, by the interface, a read command from the host; reconfiguring the write operation in response to detection of the read command during execution of the write operation; beginning execution of a read operation on a second array plane in response to the read command; and restoring the configuration of the write operation after the read operation has at least partially been executed.

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