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1. 发明授权

US09129817B2 Magnetic core inductor (MCI) structures for integrated voltage regulators 有权
标题翻译：用于集成稳压器的磁芯电感（MCI）结构
公开(公告)号：US09129817B2
公开(公告)日：2015-09-08
申请号：US13801623
申请日：2013-03-13
申请人： Adel A. Elsherbini , Kevin P. O'Brien , Henning Braunisch , Krishna Bharath
发明人： Adel A. Elsherbini , Kevin P. O'Brien , Henning Braunisch , Krishna Bharath
IPC分类号： H01L27/08 , H01L27/06 , H01L23/64 , H01L25/16 , H01L27/01 , H01L49/02
CPC分类号： H01L27/06 , H01F17/0006 , H01F2017/0066 , H01L23/64 , H01L25/16 , H01L27/016 , H01L28/10 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor packages including magnetic core inductor (MCI) structures for integrated voltage regulators are described. In an example, a semiconductor package includes a package substrate and a semiconductor die coupled to a first surface of the package substrate. The semiconductor die has a first plurality of metal-insulator-metal (MIM) capacitor layers thereon. The semiconductor package also includes a magnetic core inductor (MCI) die coupled to a second surface of the package substrate. The MCI die includes one or more slotted inductors and has a second plurality of MIM capacitor layers thereon.
摘要翻译：描述了包括集成稳压器的磁芯电感（MCI）结构的半导体封装。在一个示例中，半导体封装包括封装衬底和耦合到封装衬底的第一表面的半导体管芯。半导体管芯在其上具有第一多个金属 - 绝缘体 - 金属（MIM）电容器层。半导体封装还包括耦合到封装衬底的第二表面的磁芯电感器（MCI）裸芯片。 MCI管芯包括一个或多个开槽电感器，并且其上具有第二多个MIM电容器层。

2. 发明申请

US20140264732A1 MAGNETIC CORE INDUCTOR (MCI) STRUCTURES FOR INTEGRATED VOLTAGE REGULATORS 有权
标题翻译：集成电压调节器的磁芯电感（MCI）结构
公开(公告)号：US20140264732A1
公开(公告)日：2014-09-18
申请号：US13801623
申请日：2013-03-13
申请人： Adel A. Elsherbini , Kevin P. O'Brien , Henning Braunisch , Krishna Bharath
发明人： Adel A. Elsherbini , Kevin P. O'Brien , Henning Braunisch , Krishna Bharath
IPC分类号： H01L27/06
CPC分类号： H01L27/06 , H01F17/0006 , H01F2017/0066 , H01L23/64 , H01L25/16 , H01L27/016 , H01L28/10 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor packages including magnetic core inductor (MCI) structures for integrated voltage regulators are described. In an example, a semiconductor package includes a package substrate and a semiconductor die coupled to a first surface of the package substrate. The semiconductor die has a first plurality of metal-insulator-metal (MIM) capacitor layers thereon. The semiconductor package also includes a magnetic core inductor (MCI) die coupled to a second surface of the package substrate. The MCI die includes one or more slotted inductors and has a second plurality of MIM capacitor layers thereon.
摘要翻译：描述了包括集成稳压器的磁芯电感（MCI）结构的半导体封装。在一个示例中，半导体封装包括封装衬底和耦合到封装衬底的第一表面的半导体管芯。半导体管芯在其上具有第一多个金属 - 绝缘体 - 金属（MIM）电容器层。半导体封装还包括耦合到封装衬底的第二表面的磁芯电感器（MCI）裸芯片。 MCI管芯包括一个或多个开槽电感器，并且其上具有第二多个MIM电容器层。

3. 发明申请

US20170092412A1 PACKAGE INTEGRATED POWER INDUCTORS USING LITHOGRAPHICALLY DEFINED VIAS 审中-公开
公开(公告)号：US20170092412A1
公开(公告)日：2017-03-30
申请号：US14866852
申请日：2015-09-26
申请人： Mathew J. Manusharow , Yonggang Li , William J. Lambert , Krishna Bharath , Adel A. Elsherbini , Feras Eid , Aleksandar Aleksov , Henning Braunisch
发明人： Mathew J. Manusharow , Yonggang Li , William J. Lambert , Krishna Bharath , Adel A. Elsherbini , Feras Eid , Aleksandar Aleksov , Henning Braunisch
IPC分类号： H01F27/28 , H01F41/04 , H01F27/24
CPC分类号： H01F27/2804 , H01F17/0013 , H01F27/24 , H01F41/041 , H01F41/042 , H01F2017/0073 , H01F2017/0086 , H01F2027/2809 , H01L21/486 , H01L23/49838 , H01L28/10 , H01L2224/16227
摘要： Embodiments of the invention include inductors integrated into a package substrate that have increased thicknesses due to the use of shaped vias, and methods of forming such packages. In an embodiment of the invention an inductor may be formed in a package substrate may include a first inductor line formed on the package substrate. In some embodiments, a shaped via may be formed over the first inductor line. Additional embodiments may include a dielectric layer that is formed over the package substrate, the first inductor line and around the shaped via. In one embodiment, a second inductor line may also be formed over the shaped via. Some embodiments of the invention may include an inductor that is a spiral inductor.

4. 发明申请

US20170093007A1 Low Loss and Low Cross Talk Transmission Lines using Shaped Vias 有权
公开(公告)号：US20170093007A1
公开(公告)日：2017-03-30
申请号：US14866693
申请日：2015-09-25
申请人： Adel A. ELSHERBINI , Mathew Manusharow , Krishna Bharath , Zhichao Zhang , Yidnekachew S. Mekonnen , Aleksandar Aleksov , Henning Braunisch , Feras Eid , Javier Soto
发明人： Adel A. ELSHERBINI , Mathew Manusharow , Krishna Bharath , Zhichao Zhang , Yidnekachew S. Mekonnen , Aleksandar Aleksov , Henning Braunisch , Feras Eid , Javier Soto
IPC分类号： H01P3/08
CPC分类号： H05K1/0245 , H01P3/02 , H01P3/026 , H01P3/08 , H01P3/085 , H01P3/088
摘要： Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.

5. 发明申请

US20140217547A1 SEMICONDUCTOR PACKAGE WITH AIR CORE INDUCTOR (ACI) AND MAGNETIC CORE INDUCTOR (MCI) 审中-公开
标题翻译：具有空心电感器（ACI）和磁芯电感器（MCI）的半导体封装
公开(公告)号：US20140217547A1
公开(公告)日：2014-08-07
申请号：US13997042
申请日：2012-03-29
申请人： Adel A. Elsherbini , Krishna Bharath , Shamala A. Chickamenahalli
发明人： Adel A. Elsherbini , Krishna Bharath , Shamala A. Chickamenahalli
IPC分类号： H01L49/02
CPC分类号： H01L28/10 , H01F2017/0086 , H01L23/645 , H01L25/16 , H01L2224/16225 , H05K1/165 , H05K1/18 , H05K2201/1003
摘要： Semiconductor die packaged with air core inductors (ACIs) and magnetic core inductors (MCIs), or with multiple MCIs, are described. In a first example, a semiconductor package includes a semiconductor die, one or more air core inductors (ACIs) coupled to the semiconductor die, and one or more magnetic core inductors (MCIs) coupled to the semiconductor die. In a second example, a semiconductor package includes a semiconductor die, a first magnetic core inductor (MCI) coupled to the semiconductor die and having a first saturation current, and a second MCI coupled to the semiconductor die and having a second, different, saturation current.
摘要翻译：描述了与空心电感器（ACI）和磁芯电感器（MCI）或多个MCI封装的半导体管芯。在第一示例中，半导体封装包括半导体管芯，耦合到半导体管芯的一个或多个空心电感器（ACI）以及耦合到半导体管芯的一个或多个磁芯电感器（MCI）。在第二示例中，半导体封装包括半导体管芯，耦合到半导体管芯并具有第一饱和电流的第一磁芯电感器（MCI）和耦合到半导体管芯并具有第二不同饱和度的第二MCI 当前。

6. 发明授权

US09607947B2 Reliable microstrip routing for electronics components 有权
公开(公告)号：US09607947B2
公开(公告)日：2017-03-28
申请号：US15183645
申请日：2016-06-15
申请人： Omkar G. Karhade , Nevin Altunyurt , Kyu Oh Lee , Krishna Bharath
发明人： Omkar G. Karhade , Nevin Altunyurt , Kyu Oh Lee , Krishna Bharath
IPC分类号： H01L23/49 , H01L23/00 , H01L25/00 , H01L23/538 , H01L23/522 , H01L23/498 , H01L23/13 , H01L21/56 , H01L23/31 , H01L25/065 , H01L23/485
CPC分类号： H01L23/5381 , H01L21/563 , H01L23/13 , H01L23/3142 , H01L23/485 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L23/49894 , H01L23/5226 , H01L23/538 , H01L23/5384 , H01L23/5385 , H01L23/5386 , H01L23/562 , H01L24/17 , H01L25/0655 , H01L25/0657 , H01L2224/16145 , H01L2224/16225 , H01L2224/1703 , H01L2224/17051 , H01L2224/26175 , H01L2224/32145 , H01L2224/32225 , H01L2224/45147 , H01L2224/73204 , H01L2224/73253 , H01L2224/83385 , H01L2225/06513 , H01L2225/06517 , H01L2225/06568 , H01L2924/00011 , H01L2924/01014 , H01L2924/10253 , H01L2924/10271 , H01L2924/12042 , H01L2924/14 , H01L2924/1431 , H01L2924/14335 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/1443 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H01L2924/182 , H01L2924/37002 , H01L2924/00 , H01L2924/01033
摘要： Reliable microstrip routing arrangements for electronics components are described. In an example, a semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a semiconductor package substrate by a plurality of conductive contacts. A plurality of discrete metal planes is disposed at the uppermost metallization layer of the semiconductor package substrate, each metal plane located, from a plan view perspective, at a corner of a perimeter of the semiconductor die. Microstrip routing is disposed at the uppermost metallization layer of the semiconductor package substrate, from the plan view perspective, outside of the perimeter of the semiconductor die.

7. 发明申请

US20150001733A1 RELIABLE MICROSTRIP ROUTING FOR ELECTRONICS COMPONENTS 有权
标题翻译：电子元件可靠的微波路由
公开(公告)号：US20150001733A1
公开(公告)日：2015-01-01
申请号：US13930086
申请日：2013-06-28
申请人： Omkar G. Karhade , Nevin Altunyurt , Kyu Oh Lee , Krishna Bharath
发明人： Omkar G. Karhade , Nevin Altunyurt , Kyu Oh Lee , Krishna Bharath
IPC分类号： H01L23/538 , H01L23/522
CPC分类号： H01L23/5381 , H01L21/563 , H01L23/13 , H01L23/3142 , H01L23/485 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L23/49894 , H01L23/5226 , H01L23/538 , H01L23/5384 , H01L23/5385 , H01L23/5386 , H01L23/562 , H01L24/17 , H01L25/0655 , H01L25/0657 , H01L2224/16145 , H01L2224/16225 , H01L2224/1703 , H01L2224/17051 , H01L2224/26175 , H01L2224/32145 , H01L2224/32225 , H01L2224/45147 , H01L2224/73204 , H01L2224/73253 , H01L2224/83385 , H01L2225/06513 , H01L2225/06517 , H01L2225/06568 , H01L2924/00011 , H01L2924/01014 , H01L2924/10253 , H01L2924/10271 , H01L2924/12042 , H01L2924/14 , H01L2924/1431 , H01L2924/14335 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/1443 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H01L2924/182 , H01L2924/37002 , H01L2924/00 , H01L2924/01033
摘要： Reliable microstrip routing arrangements for electronics components are described. In an example, a semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a semiconductor package substrate by a plurality of conductive contacts. A plurality of discrete metal planes is disposed at the uppermost metallization layer of the semiconductor package substrate, each metal plane located, from a plan view perspective, at a corner of a perimeter of the semiconductor die. Microstrip routing is disposed at the uppermost metallization layer of the semiconductor package substrate, from the plan view perspective, outside of the perimeter of the semiconductor die.
摘要翻译：描述了用于电子部件的可靠的微带布线布置。在一个示例中，半导体器件包括具有其上具有集成电路的表面的半导体管芯，其通过多个导电触点耦合到半导体封装衬底的最上层金属化层的接触焊盘。多个离散金属平面设置在半导体封装基板的最上层的金属化层上，每个金属平面从平面图的角度位于半导体管芯的周边的角部。从半导体封装基板的最上层的金属化层设置微带布线，从平面图的角度来看，位于半导体管芯的外围。

8. 发明授权

US09391025B2 Reliable microstrip routing for electronics components 有权
标题翻译：电子元件可靠的微带线路
公开(公告)号：US09391025B2
公开(公告)日：2016-07-12
申请号：US14692400
申请日：2015-04-21
申请人： Omkar G. Karhade , Nevin Altunyurt , Kyu Oh Lee , Krishna Bharath
发明人： Omkar G. Karhade , Nevin Altunyurt , Kyu Oh Lee , Krishna Bharath
IPC分类号： H01L23/00 , H01L25/00 , H01L23/538 , H01L23/522 , H01L23/13 , H01L21/56 , H01L23/31 , H01L23/485 , H01L23/498 , H01L25/065
CPC分类号： H01L23/5381 , H01L21/563 , H01L23/13 , H01L23/3142 , H01L23/485 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L23/49894 , H01L23/5226 , H01L23/538 , H01L23/5384 , H01L23/5385 , H01L23/5386 , H01L23/562 , H01L24/17 , H01L25/0655 , H01L25/0657 , H01L2224/16145 , H01L2224/16225 , H01L2224/1703 , H01L2224/17051 , H01L2224/26175 , H01L2224/32145 , H01L2224/32225 , H01L2224/45147 , H01L2224/73204 , H01L2224/73253 , H01L2224/83385 , H01L2225/06513 , H01L2225/06517 , H01L2225/06568 , H01L2924/00011 , H01L2924/01014 , H01L2924/10253 , H01L2924/10271 , H01L2924/12042 , H01L2924/14 , H01L2924/1431 , H01L2924/14335 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/1443 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H01L2924/182 , H01L2924/37002 , H01L2924/00 , H01L2924/01033
摘要： Reliable microstrip routing arrangements for electronics components are described. In an example, a semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a semiconductor package substrate by a plurality of conductive contacts. A plurality of discrete metal planes is disposed at the uppermost metallization layer of the semiconductor package substrate, each metal plane located, from a plan view perspective, at a corner of a perimeter of the semiconductor die. Microstrip routing is disposed at the uppermost metallization layer of the semiconductor package substrate, from the plan view perspective, outside of the perimeter of the semiconductor die.
摘要翻译：描述了用于电子部件的可靠的微带布线布置。在一个示例中，半导体器件包括具有其上具有集成电路的表面的半导体管芯，其通过多个导电触点耦合到半导体封装衬底的最上层金属化层的接触焊盘。多个离散金属平面设置在半导体封装基板的最上层的金属化层上，每个金属平面从平面图的角度位于半导体管芯的周边的角部。从半导体封装基板的最上层的金属化层设置微带布线，从平面图的角度来看，位于半导体管芯的外围。

9. 发明授权

US08219377B2 Multi-layer finite element method for modeling of package power and ground planes 有权
标题翻译：用于建模封装电源和接地层的多层有限元法
公开(公告)号：US08219377B2
公开(公告)日：2012-07-10
申请号：US12710991
申请日：2010-02-23
申请人： Krishna Bharath , Madhavan Swaminathan
发明人： Krishna Bharath , Madhavan Swaminathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5018 , G06F2217/40
摘要： In a method for simulating electrical characteristics of a plurality of power planes, each power plane includes a plurality of geometric features. The geometric features of each power plane are projected onto a single planar construct. A polygonal mesh, including a plurality of pairs of interconnected nodes, that corresponds to the single planar construct is generated. The polygonal mesh is projected onto at least one power plane an equivalent circuit between each adjacent node of the plurality of interconnected nodes is projected onto the power plane. An equivalent capacitance is assigned between each node and a common ground planer. A finite element equation that includes a plurality of discrete terms is generated. The equation is solved, thereby determining the electrical characteristic value between each pair of adjacent nodes.
摘要翻译：在用于模拟多个电力平面的电气特性的方法中，每个电力平面包括多个几何特征。每个功率平面的几何特征投影到单个平面结构上。产生对应于单个平面构造的多边形网格，包括多对互连的节点对。将多边形网格投影到至少一个电力平面上，将多个相互连接的节点中的每个相邻节点之间的等效电路投影到电力平面上。在每个节点和公共地面刨床之间分配等效电容。生成包括多个离散项的有限元方程。解决方程式，从而确定每对相邻节点之间的电特性值。

10. 发明申请

US20100217576A1 Multi-Layer Finite Element Method for Modeling of Package Power and Ground Planes 有权
标题翻译：包层电力和地面平面建模的多层有限元方法
公开(公告)号：US20100217576A1
公开(公告)日：2010-08-26
申请号：US12710991
申请日：2010-02-23
申请人： Krishna Bharath , Madhavan Swaminathan
发明人： Krishna Bharath , Madhavan Swaminathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5018 , G06F2217/40
摘要： In a method for simulating electrical characteristics of a plurality of power planes, each power plane includes a plurality of geometric features. The geometric features of each power plane are projected onto a single planar construct. A polygonal mesh, including a plurality of pairs of interconnected nodes, that corresponds to the single planar construct is generated. The polygonal mesh is projected onto at least one power plane an equivalent circuit between each adjacent node of the plurality of interconnected nodes is projected onto the power plane. An equivalent capacitance is assigned between each node and a common ground planer. A finite element equation that includes a plurality of discrete terms is generated. The equation is solved, thereby determining the electrical characteristic value between each pair of adjacent nodes.
摘要翻译：在用于模拟多个电力平面的电气特性的方法中，每个电力平面包括多个几何特征。每个功率平面的几何特征投影到单个平面结构上。产生对应于单个平面构造的多边形网格，包括多对互连的节点对。将多边形网格投影到至少一个电力平面上，将多个相互连接的节点中的每个相邻节点之间的等效电路投影到电力平面上。在每个节点和公共地面刨床之间分配等效电容。生成包括多个离散项的有限元方程。解决方程式，从而确定每对相邻节点之间的电特性值。

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