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1. 发明授权

US4432134A Process for in-situ formation of niobium-insulator-niobium Josephson tunnel junction devices 失效
标题翻译：铌 - 绝缘体铌约瑟夫逊隧道结器件的原位形成工艺
公开(公告)号：US4432134A
公开(公告)日：1984-02-21
申请号：US376483
申请日：1982-05-10
申请人： Addison B. Jones , Francis M. Erdmann
发明人： Addison B. Jones , Francis M. Erdmann
IPC分类号： H01L39/24 , H01L39/22
CPC分类号： H01L39/2493 , Y10S505/82 , Y10S505/922 , Y10T29/49014
摘要： A method of forming a superconductor-barrier-superconductor junction device by the steps of depositing a first superconductive layer on a substrate, forming a barrier layer on the first superconductive layer and depositing a second superconductive layer on the barrier layer. A layer of photoresist is then deposited over the second superconductive layer and patterned together with the second superconductive layer to form a mesa structure. A dielectric layer is deposited over the mesa structure, and the photoresist layer portion is dissolved thereby lifting off the dielectric portion overlying said second superconductive layer portion.
摘要翻译：通过以下步骤形成超导体 - 阻挡 - 超导体结器件的方法：在衬底上沉积第一超导层，在第一超导层上形成阻挡层，并在阻挡层上沉积第二超导层。然后将一层光致抗蚀剂沉积在第二超导层上，并与第二超导层一起构图以形成台面结构。介电层沉积在台面结构的上方，并且光致抗蚀剂层部分被溶解，从而提升覆盖在所述第二超导层部分上的电介质部分。

2. 发明授权

US4279069A Fabrication of a nonvolatile memory array device 失效
标题翻译：非易失性存储器阵列器件的制造
公开(公告)号：US4279069A
公开(公告)日：1981-07-21
申请号：US13351
申请日：1979-02-21
申请人： Moiz M. E. Beguwala , Francis M. Erdmann
发明人： Moiz M. E. Beguwala , Francis M. Erdmann
IPC分类号： H01L27/112 , G11C16/04 , H01L21/8246 , H01L21/8247 , H01L21/86 , H01L27/12 , H01L29/788 , H01L29/792 , H01L21/26
CPC分类号： G11C16/0466 , H01L21/86 , H01L27/12 , Y10S257/906
摘要： There is shown and described a memory array using MNOS/MOS transistors. The memory devices are nonvolatile, metal-nitride-oxide-semiconductor (MNOS) variable threshold voltage transistors and the metal-oxide semiconductor (MOS) input-output devices exhibit fixed threshold voltages. The MOS devices are fabricated first and the MNOS memory devices are fabricated thereafter. This memory gate last (MGL) arrangement eliminates the need for high temperature process steps after the formation of the MNOS device gate dielectric in the array devices. This operation results in an MNOS/MOS memory array which exhibits excellent ionizing radiation hardness characteristics as well as memory properties which are improved over present radiation hardened MNOS/MOS arrays.
摘要翻译：显示并描述了使用MNOS / MOS晶体管的存储器阵列。存储器件是非易失性的，金属氮化物 - 氧化物半导体（MNOS）可变阈值电压晶体管，并且金属氧化物半导体（MOS）输入 - 输出器件表现出固定的阈值电压。首先制造MOS器件，之后制造MNOS存储器件。该存储器门最后（MGL）布置在阵列器件中形成MNOS器件栅极电介质之后，不需要高温处理步骤。该操作导致MNOS / MOS存储器阵列，其显示出优异的电离辐射硬度特性以及在现有辐射硬化的MNOS / MOS阵列上改善的记忆特性。

3. 发明授权

US06946200B2 Methods for reducing the curvature in boron-doped silicon micromachined structures 失效
标题翻译：减少硼掺杂硅微加工结构中曲率的方法
公开(公告)号：US06946200B2
公开(公告)日：2005-09-20
申请号：US10334588
申请日：2002-12-30
申请人： Cleopatra Cabuz , Max C. Glenn , Francis M. Erdmann , Robert D. Horning
发明人： Cleopatra Cabuz , Max C. Glenn , Francis M. Erdmann , Robert D. Horning
IPC分类号： B81B3/00 , B81C1/00 , H01L21/308 , H01L29/84 , B32B9/00
CPC分类号： B81C1/00365 , B81C2201/0164 , Y10T428/21 , Y10T428/2495
摘要： Layers of boron-doped silicon having reduced out-of-plane curvature are disclosed. The layers have substantially equal concentrations of boron near the top and bottom surfaces. Since the opposing concentrations are substantially equal, the compressive stresses on the layers are substantially balanced, thereby resulting in layers with reduced out-of-plane curvature.
摘要翻译：公开了具有减小的平面外曲率的硼掺杂硅层。这些层在顶部和底部表面附近具有基本相等的硼浓度。由于相反的浓度基本相等，所以层上的压缩应力基本平衡，从而导致具有减小的面外曲率的层。

4. 发明授权

US06544655B1 Methods for reducing the curvature in boron-doped silicon micromachined structures 失效
公开(公告)号：US06544655B1
公开(公告)日：2003-04-08
申请号：US09634932
申请日：2000-08-08
申请人： Cleopatra Cabuz , Max C. Glenn , Francis M. Erdmann , Robert D. Horning
发明人： Cleopatra Cabuz , Max C. Glenn , Francis M. Erdmann , Robert D. Horning
IPC分类号： B32B904
CPC分类号： B81C1/00365 , B81C2201/0164 , Y10T428/21 , Y10T428/2495
摘要： Layers of boron-doped silicon having reduced out-of-plane curvature are disclosed. The layers have substantially equal concentrations of boron near the top and bottom surfaces. Since the opposing concentrations are substantially equal, the compressive stresses on the layers are substantially balanced, thereby resulting in layers with reduced out-of-plane curvature.

5. 发明授权

US06969425B2 Methods for reducing the curvature in boron-doped silicon micromachined structures 失效
公开(公告)号：US06969425B2
公开(公告)日：2005-11-29
申请号：US10346887
申请日：2003-01-17
申请人： Cleopatra Cabuz , Max C. Glenn , Francis M. Erdmann , Robert D. Horning
发明人： Cleopatra Cabuz , Max C. Glenn , Francis M. Erdmann , Robert D. Horning
IPC分类号： B81B3/00 , B81C1/00 , H01L21/308 , H01L29/84 , C30B1/10
CPC分类号： B81C1/00365 , B81C2201/0164 , Y10T428/21 , Y10T428/2495
摘要： Layers of boron-doped silicon having reduced out-of-plane curvature are disclosed. The layers have substantially equal concentrations of boron near the top and bottom surfaces. Since the opposing concentrations are substantially equal, the compressive stresses on the layers are substantially balanced, thereby resulting in layers with reduced out-of-plane curvature.

6. 发明授权

US5102214A Interferometer alignment control apparatus 失效
标题翻译：干涉仪对准控制装置
公开(公告)号：US5102214A
公开(公告)日：1992-04-07
申请号：US456997
申请日：1989-12-26
申请人： Kenneth L. Steele , Thomas M. Wirt , Francis M. Erdmann , Frederick Vescial , William T. Schmars , Frederick Aronowitz
发明人： Kenneth L. Steele , Thomas M. Wirt , Francis M. Erdmann , Frederick Vescial , William T. Schmars , Frederick Aronowitz
IPC分类号： G01B7/31 , G01B9/02
CPC分类号： G01B7/31 , G01B9/0205 , G01B9/02068
摘要： An alignment and path length control apparatus having a mirror housing having a base and a closed wall. The base has a mirrored external surface. The closed wall has a central axis. The closed wall is joined to the base at a base end of the closed wall by a flexible web. The closed wall extends above the base and terminates at a rim defining an aperture. The base has a central region coupled to the cylindrical wall. A post extends from the central region of the base within the cylindrical wall to a top end. A mirror axis extends from the mirrored external surface through the post. The central axis is substantially parallel to the mirror axis. An alignment transducer responds to a first alignment control signal by applying at least a first force between the post and the wall to deflect the mirror axis with respect to the central axis. A linear transducer responds to a linear displacement control signal by applying an axial force to the post to displace the central region longitudinally along the central axis.
摘要翻译：具有镜壳体的对准和路径长度控制装置具有底座和封闭壁。底座有一个镜面外表面。封闭的墙壁有一个中心轴线。封闭的壁通过柔性纤维网在封闭壁的基端连接到基部。封闭的壁在基座之上延伸并且终止于限定孔的边缘。底座具有联接到圆柱形壁的中心区域。柱从圆柱形壁中的基部的中心区域延伸到顶端。反射镜轴从镜面的外表面延伸穿过柱。中心轴基本上平行于镜像轴。对准传感器通过在柱和壁之间施加至少一个第一力使第一对准控制信号相对于中心轴偏转反射镜轴线来响应第一对准控制信号。线性换能器通过向柱施加轴向力以沿中心轴纵向移位中心区域来响应于线性位移控制信号。

7. 发明授权

US4277320A Process for direct thermal nitridation of silicon semiconductor devices 失效
标题翻译：硅半导体器件的直接热氮化工艺
公开(公告)号：US4277320A
公开(公告)日：1981-07-07
申请号：US80859
申请日：1979-10-01
申请人： Moiz M. E. Beguwala , Francis M. Erdmann
发明人： Moiz M. E. Beguwala , Francis M. Erdmann
IPC分类号： H01L21/318 , C01B21/068 , B05D3/06 , H01L7/00
CPC分类号： H01L21/3185
摘要： A process for the direct thermal nitridation of silicon semiconductor devices in which the semiconductor body is placed in an atmosphere of N.sub.2, at a temperature of less than 1000.degree. C. The N.sub.2 is activated by an RF electrical field which ionizes the nitrogen, which then combines with the silicon surface.
摘要翻译：一种用于将半导体体放置在N2气氛中的硅半导体器件的直接热氮化处理，温度低于1000℃.N2由RF电场激活，该电场使氮离子化结合硅表面。

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