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1. 发明申请

US20130159674A1 INSTRUCTION PREDICATION USING INSTRUCTION FILTERING 有权
标题翻译：使用指导性过滤的指导性预测
公开(公告)号：US20130159674A1
公开(公告)日：2013-06-20
申请号：US13329575
申请日：2011-12-19
申请人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F9/38 , G06F9/312
CPC分类号： G06F9/30072 , G06F9/30101 , G06F9/30185
摘要： A method and circuit arrangement for selectively predicating instructions in an instruction stream based upon a predication filter criteria defined by a predication filter, which describes types or patterns of instructions that should be predicated. Predication logic compares a respective instruction of an instruction stream to predication filter criteria to determine whether the respective instruction matches the predication filter criteria, and the respective instruction is selectively predicated based on whether the respective instruction matches the predication filter criteria.
摘要翻译：一种用于基于由预测滤波器定义的预测滤波器标准来选择性地在指令流中预测指令的方法和电路装置，其描述应该被预测的指令的类型或模式。预测逻辑将指令流的相应指令与预测过滤器标准进行比较，以确定各个指令是否与预测过滤器标准相匹配，并且基于各个指令是否匹配预测过滤器标准来选择性地预测相应的指令。

2. 发明授权

US08102884B2 Direct inter-thread communication buffer that supports software controlled arbitrary vector operand selection in a densely threaded network on a chip 失效
标题翻译：直接跨线程通信缓冲器，支持在芯片上密集线程网络中软件控制的任意向量操作数选择
公开(公告)号：US08102884B2
公开(公告)日：2012-01-24
申请号：US12251528
申请日：2008-10-15
申请人： Adam J. Muff , Robert A. Shearer , Matthew R. Tubbs
发明人： Adam J. Muff , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： H04J3/04
CPC分类号： H04L49/10 , H04L49/109 , H04L49/15
摘要： A computer-implemented method, system and computer program product for retrieving arbitrarily aligned vector operands within a highly threaded Network On a Chip (NOC) processor are presented. Multiple nodes in a NOC are able to access a single Compressed Direct Interthread Communication Buffer (CDICB), which contains a misaligned but compacted set of operands. Using information from a Special Purpose Register (SPR) within the NOC, each node is able to selectively extract one or more operands from the CDICB for use in an execution unit within that node. Output from the execution unit is then sent to the CDICB to update the compacted set of operands.
摘要翻译：提出了一种计算机实现的方法，系统和计算机程序产品，用于检索高度线程的片上网络（NOC）处理器内的任意对齐的向量操作数。 NOC中的多个节点能够访问单个压缩直接通信间通信缓冲器（CDICB），它包含一个不对齐但压缩的操作数集合。使用NOC中特殊目的寄存器（SPR）的信息，每个节点都能够有选择地从CDICB中提取一个或多个操作数，以便在该节点内的执行单元中使用。然后将执行单元的输出发送到CDICB以更新压缩的一组操作数。

3. 发明授权

US07873066B2 Streaming direct inter-thread communication buffer packets that support hardware controlled arbitrary vector operand alignment in a densely threaded network on a chip 失效
标题翻译：在芯片上的密集线程网络中支持硬件控制的任意向量操作数对齐的流式直接跨线程通信缓冲包
公开(公告)号：US07873066B2
公开(公告)日：2011-01-18
申请号：US12359777
申请日：2009-01-26
申请人： Adam J. Muff , Robert A. Shearer , Matthew R. Tubbs
发明人： Adam J. Muff , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： H04L12/54 , H04J3/18 , G06F7/00 , G06F13/38
CPC分类号： G06F9/546 , G06F9/30109 , G06F9/30174 , G06F9/384 , G06F9/3842 , G06F9/3844 , G06F9/3855 , G06F9/3857 , G06F9/3885
摘要： A computer-implemented method, system and computer program product for arbitrarily aligning vector operands, which are transmitted in inter-thread communication buffer packets within a highly threaded Network On a Chip (NOC) processor, are presented. A set of multiplexers in a node in the NOC realigns and extracts data word aggregations from an incoming compressed inter-thread communication buffer packet. The extracted data word aggregations are used as operands by an execution unit within the node.
摘要翻译：提出了一种用于任意对齐向量操作数的计算机实现的方法，系统和计算机程序产品，其在高度线程的片上网络片上（NOC）处理器内的线程间通信缓冲器包中传送。 NOC中的节点中的一组多路复用器重新对齐并从输入的压缩的线间通信缓冲包中提取数据字聚合。提取的数据字聚合由节点内的执行单元用作操作数。

4. 发明申请

US20100106940A1 Processing Unit With Operand Vector Multiplexer Sequence Control 有权
标题翻译：具有操作数向量多路复用器序列控制的处理单元
公开(公告)号：US20100106940A1
公开(公告)日：2010-04-29
申请号：US12256550
申请日：2008-10-23
申请人： Adam J. Muff , Robert A. Shearer , Matthew R. Tubbs
发明人： Adam J. Muff , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F15/76 , G06F9/30
CPC分类号： G06F9/30036 , G06F9/30032 , G06F9/30145 , G06F9/3851
摘要： Operand vector multiplexer sequence control is used in a vector-based execution unit to control the shuffling of data elements in operand vectors used by a sequence of vector instructions processed by the vector-based execution unit. A swizzle sequence instruction is defined in an instruction set for the vector-based execution unit and is used to selectively apply a sequence of vector data element shuffle orders to one or more operand vectors to be used by the associated sequence of vector instructions. As a result, when a common sequence of data element shuffle orders is used frequently for a sequence of vector instructions, a single swizzle sequence instruction may be used to select the desired sequence of custom data element ordering for each of the vector instructions in the sequence.
摘要翻译：操作数向量复用器序列控制在基于向量的执行单元中用于控制由基于向量的执行单元处理的向量指令序列使用的操作数向量中的数据元素的混洗。在用于基于矢量的执行单元的指令集中定义了一个旋转序列指令，并且用于向量数据元素洗牌顺序的一个或多个操作数向量选择性地应用以由相关的向量指令序列使用。结果，当对于一系列向量指令频繁使用数据元素随机顺序的公共序列时，可以使用单个交换序列指令来选择序列中每个向量指令的定制数据元素排序的期望序列。

5. 发明授权

US09632779B2 Instruction predication using instruction filtering 有权
公开(公告)号：US09632779B2
公开(公告)日：2017-04-25
申请号：US13329575
申请日：2011-12-19
申请人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F9/30
CPC分类号： G06F9/30072 , G06F9/30101 , G06F9/30185
摘要： A method and circuit arrangement for selectively predicating instructions in an instruction stream based upon a predication filter criteria defined by a predication filter, which describes types or patterns of instructions that should be predicated. Predication logic compares a respective instruction of an instruction stream to predication filter criteria to determine whether the respective instruction matches the predication filter criteria, and the respective instruction is selectively predicated based on whether the respective instruction matches the predication filter criteria.

6. 发明授权

US09032191B2 Virtualization support for branch prediction logic enable / disable at hypervisor and guest operating system levels 有权
标题翻译：分支预测逻辑的虚拟化支持在管理程序和客户机操作系统级别启用/禁用
公开(公告)号：US09032191B2
公开(公告)日：2015-05-12
申请号：US13355863
申请日：2012-01-23
申请人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F9/38
CPC分类号： G06F9/3848 , G06F9/3842 , G06F9/3844 , G06F9/45558
摘要： A hypervisor and one or more guest operating systems resident in a data processing system and hosted by the hypervisor are configured to selectively enable or disable branch prediction logic through separate hypervisor-mode and guest-mode instructions. By doing so, different branch prediction strategies may be employed for different operating systems and user applications hosted thereby to provide finer grained optimization of the branch prediction logic for different operating scenarios.
摘要翻译：驻留在数据处理系统中并由管理程序托管的管理程序和一个或多个客户操作系统被配置为通过单独的管理程序模式和访客模式指令选择性地启用或禁用分支预测逻辑。通过这样做，不同的分支预测策略可以用于托管的不同操作系统和用户应用，从而为不同的操作场景提供分支预测逻辑的更细粒度优化。

7. 发明授权

US08892851B2 Changing opcode of subsequent instruction when same destination address is not used as source address by intervening instructions 有权
标题翻译：当相同的目的地址不通过介入指令用作源地址时，更改随后指令的操作码
公开(公告)号：US08892851B2
公开(公告)日：2014-11-18
申请号：US13287412
申请日：2011-11-02
申请人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F9/318 , G06F9/30
CPC分类号： G06F9/30 , G06F9/30145 , G06F9/30181 , G06F9/3832
摘要： A circuit arrangement and method support compression and expansion of instruction opcodes by detecting successive address targeting and decoding a first opcode of an instruction into a second opcode in response to detecting successive address targeting. The circuit arrangement and method execute instructions in an instruction stream and detect successive address targeting by two or more instructions in the instruction stream without the targeted address being utilized as a source address in an instruction executed between the first and second instructions in the instruction stream. Then, based on that detection, the opcode of the second instruction is modified, changed, or appended to such that a different opcode is indicated by the second instruction, such that executing the second instruction causes a different unique type of operation to be performed.
摘要翻译：电路布置和方法通过响应于检测到连续的地址目标来检测连续的地址目标和将指令的第一操作码解码成第二操作码来支持指令操作码的压缩和扩展。电路装置和方法在指令流中执行指令，并且在指令流中的指令流中的第一和第二指令之间执行的指令中，用目标地址作为源地址来检测指令流中两个或多个指令的连续地址定向。然后，基于该检测，第二指令的操作码被修改，改变或附加，使得由第二指令指示不同的操作码，使得执行第二指令导致执行不同的独特类型的操作。

8. 发明授权

US08549262B2 Instruction operand addressing using register address sequence detection 失效
标题翻译：指令操作数寻址使用寄存器地址序列检测
公开(公告)号：US08549262B2
公开(公告)日：2013-10-01
申请号：US12778635
申请日：2010-05-12
申请人： Eric O. Mejdrich , Adam J. Muff , Robert A. Shearer , Matthew R. Tubbs
发明人： Eric O. Mejdrich , Adam J. Muff , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F9/30
CPC分类号： G06F9/30065 , G06F9/30098 , G06F9/30101 , G06F9/3016
摘要： A circuit arrangement and method support efficient indexing into large register files by utilizing register address sequence detection, wherein register addresses to be used by an instruction are produced by concatenating a portion of the address that is contained in the instruction with another portion that is speculatively produced by sequence detection logic. The portion of the correct full address that is not contained in the instruction is stored in a software accessible special purpose register. If the end of a particular sequence of addresses is detected by the sequence detection logic, the invention speculatively assumes that the next address in the sequence will be used. Since only a portion of the full addresses are stored in the instruction, they occupy less instruction space than the full address widths. An instruction may include at least one address portion that identifies a register address.
摘要翻译：电路布置和方法通过利用寄存器地址序列检测来支持对大型寄存器文件的高效索引，其中由指令使用的寄存器地址是通过将指令中包含的地址的一部分连接到被推测产生的另一部分来产生的通过序列检测逻辑。指令中未包含的正确完整地址的部分存储在软件可访问的专用寄存器中。如果由序列检测逻辑检测到特定地址序列的结尾，则本发明推测地假定序列中的下一个地址将被使用。由于只有一部分完整地址存储在指令中，所以占用的地址宽度比完整地址少。指令可以包括标识寄存器地址的至少一个地址部分。

9. 发明申请

US20130191824A1 VIRTUALIZATION SUPPORT FOR BRANCH PREDICTION LOGIC ENABLE/DISABLE 有权
标题翻译：支持分支预测逻辑的虚拟化支持启用/禁用
公开(公告)号：US20130191824A1
公开(公告)日：2013-07-25
申请号：US13355863
申请日：2012-01-23
申请人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F9/455
CPC分类号： G06F9/3848 , G06F9/3842 , G06F9/3844 , G06F9/45558
摘要： A hypervisor and one or more guest operating systems resident in a data processing system and hosted by the hypervisor are configured to selectively enable or disable branch prediction logic through separate hypervisor-mode and guest-mode instructions. By doing so, different branch prediction strategies may be employed for different operating systems and user applications hosted thereby to provide finer grained optimization of the branch prediction logic for different operating scenarios.
摘要翻译：驻留在数据处理系统中并由管理程序托管的管理程序和一个或多个客户操作系统被配置为通过单独的管理程序模式和访客模式指令选择性地启用或禁用分支预测逻辑。通过这样做，不同的分支预测策略可以用于托管的不同操作系统和用户应用，从而为不同的操作场景提供分支预测逻辑的更细粒度优化。

10. 发明申请

US20110283090A1 Instruction Addressing Using Register Address Sequence Detection 失效
标题翻译：指令寻址使用寄存器地址序列检测
公开(公告)号：US20110283090A1
公开(公告)日：2011-11-17
申请号：US12778635
申请日：2010-05-12
申请人： Eric O. Mejdrich , Adam J. Muff , Robert A. Shearer , Matthew R. Tubbs
发明人： Eric O. Mejdrich , Adam J. Muff , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F9/30
CPC分类号： G06F9/30065 , G06F9/30098 , G06F9/30101 , G06F9/3016
摘要： A circuit arrangement and method support efficient indexing into large register files by utilizing register address sequence detection, wherein register addresses to be used by an instruction are produced by concatenating a portion of the address that is contained in the instruction with another portion that is speculatively produced by sequence detection logic. The portion of the correct full address that is not contained in the instruction is stored in a software accessible special purpose register. If the end of a particular sequence of addresses is detected by the sequence detection logic, the invention speculatively assumes that the next address in the sequence will be used. Since only a portion of the full addresses are stored in the instruction, they occupy less instruction space than the full address widths. An instruction may include at least one address portion that identifies a register address.
摘要翻译：电路布置和方法通过利用寄存器地址序列检测来支持对大型寄存器文件的有效索引，其中由指令使用的寄存器地址是通过将指令中包含的地址的一部分连接到被推测产生的另一部分来产生的通过序列检测逻辑。指令中未包含的正确完整地址的部分存储在软件可访问的专用寄存器中。如果由序列检测逻辑检测到特定地址序列的结尾，则本发明推测地假定序列中的下一个地址将被使用。由于只有一部分完整地址存储在指令中，所以占用的地址宽度比完整地址少。指令可以包括标识寄存器地址的至少一个地址部分。

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