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1. 发明授权

US06445423B1 Controlled oscillator in a digital symbol timing recovery network 有权
标题翻译：数字符号定时恢复网络中的受控振荡器
公开(公告)号：US06445423B1
公开(公告)日：2002-09-03
申请号：US09351065
申请日：1999-07-09
申请人： Aaron Reel Bouillet , David Glen White
发明人： Aaron Reel Bouillet , David Glen White
IPC分类号： H04N5455
CPC分类号： H03L7/091 , H03L7/10 , H03L2207/06 , H04L25/03019 , H04L27/066 , H04L2025/03598 , H04L2025/03732 , H04L2027/0036 , H04L2027/0038 , H04L2027/0087 , H04N5/126
摘要： A receiver for processing a VSB modulated signal containing terrestrial broadcast high definition television information includes an input analog-to-digital converter (19) for producing a digital datastream. A symbol timing recovery and segment sync recovery network (24; FIG. 3, 4) develops a properly timed sampling clock for the digital converter (19). The symbol timing recovery network (310) responds to an output from the segment sync recovery network (328), which in turn responds to an equalized signal from an adaptive channel equalizer (34). A controlled oscillator (336) generates the sampling clock for the digital converter. A control network (340, 344, 348; FIG. 3) shifts the frequency range of the oscillator to maintain desired linear operation to enhance symbol timing acquisition.
摘要翻译：一种用于处理包含地面广播高分辨率电视信息的VSB调制信号的接收机包括用于产生数字数据流的输入模拟 - 数字转换器（19）。符号定时恢复和段同步恢复网络（24;图3，4）为数字转换器（19）开发适当定时的采样时钟。符号定时恢复网络（310）响应来自段同步恢复网络（328）的输出，其响应于来自自适应信道均衡器（34）的均衡信号。受控振荡器（336）产生数字转换器的采样时钟。控制网络（340,344,348;图3）移动振荡器的频率范围以维持期望的线性操作以增强符号定时获取。

2. 发明授权

US09397772B2 Reliable diversity architecture for a mobile DTV system 有权
标题翻译：可移动DTV系统的可靠分集架构
公开(公告)号：US09397772B2
公开(公告)日：2016-07-19
申请号：US13511692
申请日：2009-12-03
申请人： Ivonete Markman , Aaron Reel Bouillet , Scott Matthew LoPresto
发明人： Ivonete Markman , Aaron Reel Bouillet , Scott Matthew LoPresto
IPC分类号： H04N7/64 , H04H60/11 , H04L1/00 , H04H40/18
CPC分类号： H04H60/11 , H04H40/18 , H04L1/0057
摘要： A digital data stream comprises alternating groups of information blocks and groups of parity blocks, each group of information blocks includes multiple information blocks and each group of parity blocks includes multiple parity blocks. An apparatus for receiving a digital data stream comprises a demodulator that receives and demodulates a digital data stream. An equalizer compensates for distortions in the digital data stream. A delay buffer generates a first stream of digital data representing the compensated digital data stream and a second stream of digital data representing a delayed version of the compensated digital data stream. A forward error correction block receives and processes the first and second streams of digital data from the delay buffer, and outputs an error corrected stream of digital data. A transport block receives and processes the error corrected stream from the forward error correction block for display.
摘要翻译：数字数据流包括交替的信息块组和奇偶校验块组，每组信息块包括多个信息块，并且每组奇偶校验块包括多个奇偶校验块。一种用于接收数字数据流的装置，包括接收和解调数字数据流的解调器。均衡器补偿数字数据流中的失真。延迟缓冲器产生表示补偿的数字数据流的第一数字数据流和表示经补偿的数字数据流的延迟版本的第二数字数据流。前向纠错块从延迟缓冲器接收并处理第一和第二数字数据流，并输出纠错的数字数据流。传输块从前向纠错块接收并处理纠错流，以进行显示。

3. 发明授权

US07230654B2 Channel acquisition processing for a television receiver 有权
标题翻译：电视接收机的频道采集处理
公开(公告)号：US07230654B2
公开(公告)日：2007-06-12
申请号：US10511645
申请日：2003-04-14
申请人： Weixiao Liu , Aaron Reel Bouillet , Matthew Thomas Mayer
发明人： Weixiao Liu , Aaron Reel Bouillet , Matthew Thomas Mayer
IPC分类号： H04N5/455
CPC分类号： H04L27/066 , H04L2027/003 , H04L2027/0053 , H04L2027/0071 , H04N5/4401 , H04N5/50
摘要： Channel acquisition in a digital television signal receiver is improved by determining the carrier tracking loop frequency offsets and the symbol timing recovery offsets for each channel in the television receiver. Offsets are stored in respective EEPROMs for each channel. When a channel is to be acquired in the TV receiver the tune command will be applied to the appropriate EEPROMs and the respective values are conveyed to the VSB demodulator to start acquisition of the channel.
摘要翻译：通过确定电视接收机中每个频道的载波跟踪环路频率偏移和符号定时恢复偏移来改善数字电视信号接收机中的频道采集。偏移量存储在每个通道的相应EEPROM中。当在TV接收机中要采集频道时，调谐命令将被应用于适当的EEPROM，并将相应的值传送到VSB解调器以开始获取频道。

4. 发明授权

US08237494B2 Apparatus and method for determination of signal format 有权
标题翻译：用于确定信号格式的装置和方法
公开(公告)号：US08237494B2
公开(公告)日：2012-08-07
申请号：US12737028
申请日：2009-06-03
申请人： Aaron Reel Bouillet , Mark Francis Rumreich
发明人： Aaron Reel Bouillet , Mark Francis Rumreich
IPC分类号： H03D3/00
CPC分类号： H04L27/0012 , H04L27/0008
摘要： The determination of the signal modulation format for a channel is an important aspect of the operation of a signal receiver. A method (700) is described including the steps of receiving (710) a signal, comparing (720) a sample of the received signal to a first threshold value and a second threshold value, creating (720) a signal profile based on the comparison, and selecting (750) a modulation format for the received signal based on the signal profile. An apparatus (500) is also described including a ring counter (510) that receives a sample of an input signal, compares the sample to a first threshold value and a second threshold value, and creates a signal profile for the input signal, a signal profiler (550) that compares the signal profile for the input signal to at least two reference profiles, and a detector (560) that determines a modulation format for the input signal based on the comparison in the signal profiler (550).
摘要翻译：信道的信号调制格式的确定是信号接收机的操作的重要方面。描述了一种方法（700），其包括以下步骤：接收（710）信号，将接收到的信号的样本与第一阈值和第二阈值进行比较（720），基于比较创建（720）信号分布，并且基于所述信号简档来选择（750）所述接收信号的调制格式。还描述了一种装置（500），其包括接收输入信号的样本的环形计数器（510），将样本与第一阈值和第二阈值进行比较，并且产生用于输入信号的信号分布，信号分析器（550），其将输入信号的信号分布与至少两个参考分布进行比较;以及检测器（560），其基于信号分析器（550）中的比较确定输入信号的调制格式。

5. 发明授权

US07706490B2 Analog to digital converter clock synchronizer 有权
标题翻译：模数转换器时钟同步器
公开(公告)号：US07706490B2
公开(公告)日：2010-04-27
申请号：US10587287
申请日：2004-02-02
申请人： Aaron Reel Bouillet
发明人： Aaron Reel Bouillet
IPC分类号： H04L7/00
CPC分类号： H03L7/00 , H03K5/135 , H03K5/1565 , H04L7/0025 , H04L7/033
摘要： The present application generally relates to apparatuses such as television signal processing apparatus that process radio frequency signals. More specifically, the present application is particularly useful in integrated circuits that must receive a radio frequency signal and simultaneously use circuitry where the timing of the operations are based on the received RF signal and circuitry where the timing is based on a fixed rate signal with sensitivity to clock jitter. According to an exemplary embodiment, the apparatus comprises, a first input (RefClk), a second input (PllClk), an output (CLK 1X), a delay means (405, 410, 415, 420, 425), and a logic means (430, 435, 440, 445, 450, 455, 460, 465, and 470) to compare a plurality of stages of said delay means to produce an signal at said output.
摘要翻译：本申请一般涉及诸如处理射频信号的电视信号处理装置之类的装置。更具体地，本申请在必须接收射频信号并且同时使用操作的定时基于接收到的RF信号的电路和其中定时基于具有灵敏度的固定速率信号的电路的集成电路中特别有用时钟抖动。根据示例性实施例，该装置包括第一输入（RefClk），第二输入（P11Clk），输出（CLK1X），延迟装置（405,410,415,420,425）和逻辑装置（430,435,440,445,450,455,460,465和470）以比较所述延迟装置的多个级以在所述输出端产生信号。

6. 发明申请

US20080272813A1 Analog To Digital Converter Clock Synchronizer 有权
标题翻译：模数转换器时钟同步器
公开(公告)号：US20080272813A1
公开(公告)日：2008-11-06
申请号：US10587287
申请日：2004-02-02
申请人： Aaron Reel Bouillet
发明人： Aaron Reel Bouillet
IPC分类号： H03L7/00
CPC分类号： H03L7/00 , H03K5/135 , H03K5/1565 , H04L7/0025 , H04L7/033
摘要： The present application generally relates to apparatuses such as television signal processing apparatus that process radio frequency signals. More specifically, the present application is particularly useful in integrated circuits that must receive a radio frequency signal and simultaneously use circuitry where the timing of the operations are based on the received RF signal and circuitry where the timing is based on a fixed rate signal with sensitivity to clock jitter. According to an exemplary embodiment, the apparatus comprises, a first input (RefClk), a second input (PllClk), an output (CLK 1X), a delay means (405, 410, 415, 420, 425), and a logic means (430, 435, 440, 445, 450, 455, 460, 465, and 470) to compare a plurality of stages of said delay means to produce an signal at said output.
摘要翻译：本申请一般涉及诸如处理射频信号的电视信号处理装置之类的装置。更具体地，本申请在必须接收射频信号并且同时使用操作的定时基于接收到的RF信号的电路和其中定时基于具有灵敏度的固定速率信号的电路的集成电路中特别有用时钟抖动。根据示例性实施例，该装置包括第一输入（RefClk），第二输入（P11Clk），输出（CLK1X），延迟装置（405,410,415,420,425）和逻辑用于比较所述延迟装置的多个级以在所述输出处产生信号的装置（430,435,440,445,450,455,460,465和470）。

7. 发明授权

US06985192B1 Selective gain adjustment to aid carrier acquisition in a high definition television receiver 有权
标题翻译：选择性增益调整，以帮助高清晰度电视接收机中的载波采集
公开(公告)号：US06985192B1
公开(公告)日：2006-01-10
申请号：US10031020
申请日：2000-07-13
申请人： Aaron Reel Bouillet , John Sidney Stewart
发明人： Aaron Reel Bouillet , John Sidney Stewart
IPC分类号： H04N5/50
CPC分类号： H04L27/08 , H04L2027/0057 , H04L2027/0087 , H04N5/4401 , H04N5/455 , H04N5/52
摘要： In a receiver for processing a vestigial sideband modulated signal containing terrestrial broadcast high definition television information and a pilot component, and for which multipath interference can lead to significant attenuation within narrow bands of the received signal spectrum containing the pilot tone of an Advanced Television Systems Committee high definition television broadcast signal, it has been found desirable to amplify the input signal in order to achieve synchronization of the receiver's phase-locked loop to the received pilot tone. Once this initial acquisition has been established, the amplification applied to the received signal can be reduced to a level appropriate for remaining blocks in the demodulation chain without upsetting the pilot tone synchronization. Thus, according to the present invention, the gain applied to the received ATSC VSB signal is set higher during pilot tone acquisition than it is during the remaining stages of demodulation.
摘要翻译：在用于处理包含地面广播高分辨率电视信息和导频分量的残留边带调制信号的接收机中，并且多径干扰可以导致包含高级电视系统委员会的导频音的接收信号频谱的窄带内的显着衰减高分辨率电视广播信号，已经发现放大输入信号是为了实现接收机的锁相环与所接收的导频音的同步。一旦建立了该初始采集，则可以将施加到接收信号的放大率减小到适于解调链中的剩余块的电平，而不会使导频音同步失真。因此，根据本发明，在导频音调获取期间，应用于接收到的ATSC VSB信号的增益比在剩余的解调阶段期间被设置得更高。

8. 发明授权

US06490007B1 Adaptive channel equalizer 有权
标题翻译：自适应信道均衡器
公开(公告)号：US06490007B1
公开(公告)日：2002-12-03
申请号：US09566159
申请日：2000-05-05
申请人： Aaron Reel Bouillet , Matthew Thomas Mayer , John Sidney Stewart
发明人： Aaron Reel Bouillet , Matthew Thomas Mayer , John Sidney Stewart
IPC分类号： H04N521
CPC分类号： H04N5/211 , H04L25/03038 , H04L2025/03382 , H04L2025/0363 , H04L2025/03687 , H04N5/4401
摘要： In a receiver for processing a VSB modulated signal containing terrestrial broadcast high definition television information including data packets, the received signal is converted to a digital signal (19), demodulated (22) and equalized by an adaptive channel equalizer (34). An equalized signal is processed by decoding networks including a Reed-Solomon FEC error detecting and correcting network (44). The equalizer filter coefficient step size is dynamically adjusted during the adaption process as a function of the packet error rate. A local microcontroller (60) monitors the packet error rate at the Reed-Solomon error detector and instructs the equalizer to adjust the coefficient step size in a direction to reduce the packet error rate.
摘要翻译：在用于处理包含包含数据分组的地面广播高清晰度电视信息的VSB调制信号的接收机中，接收信号被转换成数字信号（19），由自适应信道均衡器（34）解调（22）并均衡。通过解码包括Reed-Solomon FEC错误检测和校正网络（44）的网络来处理均衡的信号。均衡器滤波器系数步长在适应过程中作为分组错误率的函数进行动态调整。本地微控制器（60）监视Reed-Solomon误差检测器的分组错误率，并指示均衡器沿一个方向调整系数步长以减小分组错误率。

9. 发明申请

US20110074500A1 APPARATUS AND METHOD FOR DETERMINATION OF SIGNAL FORMAT 有权
标题翻译：用于确定信号格式的装置和方法
公开(公告)号：US20110074500A1
公开(公告)日：2011-03-31
申请号：US12737028
申请日：2009-06-03
申请人： Aaron Reel Bouillet , Mark Francis Rumreich
发明人： Aaron Reel Bouillet , Mark Francis Rumreich
IPC分类号： H03D1/00 , H03K5/22
CPC分类号： H04L27/0012 , H04L27/0008
摘要： The determination of the signal modulation format for a channel is an important aspect of the operation of a signal receiver. A method (700) is described including the steps of receiving (710) a signal, comparing (720) a sample of the received signal to a first threshold value and a second threshold value, creating (720) a signal profile based on the comparison, and selecting (750) a modulation format for the received signal based on the signal profile. An apparatus (500) is also described including a ring counter (510) that receives a sample of an input signal, compares the sample to a first threshold value and a second threshold value, and creates a signal profile for the input signal, a signal profiler (550) that compares the signal profile for the input signal to at least two reference profiles, and a detector (560) that determines a modulation format for the input signal based on the comparison in the signal profiler (550).
摘要翻译：信道的信号调制格式的确定是信号接收机的操作的重要方面。描述了一种方法（700），其包括以下步骤：接收（710）信号，将接收到的信号的样本与第一阈值和第二阈值进行比较（720），基于比较创建（720）信号分布，并且基于所述信号简档来选择（750）所述接收信号的调制格式。还描述了一种装置（500），其包括接收输入信号的样本的环形计数器（510），将样本与第一阈值和第二阈值进行比较，并且产生用于输入信号的信号分布，信号分析器（550），其将输入信号的信号分布与至少两个参考分布进行比较;以及检测器（560），其基于信号分析器（550）中的比较确定输入信号的调制格式。

10. 发明授权

US07809066B2 Packet error signal generator 有权
标题翻译：分组错误信号发生器
公开(公告)号：US07809066B2
公开(公告)日：2010-10-05
申请号：US10511654
申请日：2003-04-11
申请人： Aaron Reel Bouillet , Matthew Thomas Mayer
发明人： Aaron Reel Bouillet , Matthew Thomas Mayer
IPC分类号： H04N7/12
CPC分类号： H04L1/0057 , H04L1/0041 , H04L1/0045 , H04L1/006 , H04L27/066 , H04L2025/03382 , H04N5/4401 , H04N21/2383 , H04N21/4382
摘要： A software packet error system for a High Definition Television (HDTV) receiver. A data packet error signal is transferred from a forward error correcting Reed-Solomon decoder to a transport processor. In response to a segment sync signal, the transport processor generates an error signal which appears on a programmable output pin. The software packet error signal is synchronized with the outgoing data packet signal such that each data packet is bracketed or framed by its associating packet error signal. Precession of the start of the data packets forwarded on the transport but relative to the start of the data packets appearing at the output of the decoder occurs as a result of a training packet generated for every 312 data packets. The precession is reset at the beginning of every field and is predictable across the field duration with sufficient accuracy to make the software packet error mechanism feasible.
摘要翻译：用于高分辨率电视（HDTV）接收机的软件分组错误系统。数据分组误差信号从前向纠错Reed-Solomon解码器传送到传输处理器。响应于段同步信号，传输处理器产生出现在可编程输出引脚上的错误信号。软件分组错误信号与输出数据分组信号同步，使得每个数据分组被包围或由其关联分组误差信号构成。作为对于每312个数据分组产生的训练分组的结果，在传输上转发但相对于出现在解码器的输出端的数据分组的开始的数据分组的开始的进位发生。进场在每个场的开始被重置，并且在足够的准确度的整个场持续时间内是可预测的，以使得软件分组错误机制成为可能。

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