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1. 发明授权

US07879659B2 Methods of fabricating semiconductor devices including dual fin structures 有权
标题翻译：制造包括双鳍结构的半导体器件的方法
公开(公告)号：US07879659B2
公开(公告)日：2011-02-01
申请号：US11778938
申请日：2007-07-17
申请人： Aaron R. Wilson , Larson Lindholm , David Hwang
发明人： Aaron R. Wilson , Larson Lindholm , David Hwang
IPC分类号： H01L21/00
CPC分类号： H01L21/76224 , H01L29/66795 , H01L29/7853
摘要： Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of the substrate between the pair of STI structures, and recessing the STI structures so that the resulting dual fin structure protrudes from an active surface of the substrate. The dual fin structure may be used to form single-gate, double-gate or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.
摘要翻译： Fin-FET（鳍场效应晶体管）器件及其制造方法。 Fin-FET器件包括双鳍结构，其可以在源极区域和漏极区域之间形成沟道区域。在一些实施例中，通过形成浅沟槽隔离结构，使用一对浅沟槽隔离（STI）结构作为掩模来形成双鳍结构，以在所述一对STI结构之间的衬底的一部分中限定凹陷，以及凹陷 STI结构使得所得到的双翅片结构从基板的有效表面突出。双鳍结构可用于形成单栅极，双栅极或三栅极鳍FET器件。还公开了包括这种鳍式FET器件的电子系统。

2. 发明授权

US08138526B2 Semiconductor structures including dual fins 有权
标题翻译：半导体结构包括双鳍
公开(公告)号：US08138526B2
公开(公告)日：2012-03-20
申请号：US12944529
申请日：2010-11-11
申请人： Aaron R. Wilson , Larson Lindholm , David Hwang
发明人： Aaron R. Wilson , Larson Lindholm , David Hwang
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L29/66795 , H01L29/7853
摘要： Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by thinning shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of the substrate between the pair of STI structures, and recessing the pair of STI structures so that the resulting dual fin structure protrudes from an active surface of the substrate. The dual fin structure may be used to form single-gate, double-gate or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.
摘要翻译： Fin-FET（鳍场效应晶体管）器件及其制造方法。 Fin-FET器件包括双鳍结构，其可以在源极区域和漏极区域之间形成沟道区域。在一些实施例中，通过使用一对浅沟槽隔离（STI）结构作为掩模来减薄浅沟槽隔离结构来形成双鳍结构，以在该一对STI结构之间限定衬底的一部分中的凹陷，以及凹陷所述一对STI结构使得所得到的双翅片结构从所述基板的有源表面突出。双鳍结构可用于形成单栅极，双栅极或三栅极鳍FET器件。还公开了包括这种鳍式FET器件的电子系统。

3. 发明申请

US20090026530A1 METHODS OF FABRICATING DUAL FIN STRUCTURES AND SEMICONDUCTOR DEVICE STRUCTURES WITH DUAL FINS 有权
标题翻译：双金属结构与半导体器件结构的制作方法
公开(公告)号：US20090026530A1
公开(公告)日：2009-01-29
申请号：US11778938
申请日：2007-07-17
申请人： Aaron R. Wilson , Larson Lindholm , David Hwang
发明人： Aaron R. Wilson , Larson Lindholm , David Hwang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/76224 , H01L29/66795 , H01L29/7853
摘要： Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of the substrate between the pair of STI structures, and recessing the STI structures so that the resulting dual fin structure protrudes from an active surface of the substrate. The dual fin structure may be used to form single-gate, double-gate or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.
摘要翻译： Fin-FET（鳍场效应晶体管）器件及其制造方法。 Fin-FET器件包括双鳍结构，其可以在源极区域和漏极区域之间形成沟道区域。在一些实施例中，通过形成浅沟槽隔离结构，使用一对浅沟槽隔离（STI）结构作为掩模来形成双鳍结构，以在所述一对STI结构之间的衬底的一部分中限定凹陷，以及凹陷 STI结构使得所得到的双翅片结构从基板的有效表面突出。双鳍结构可用于形成单栅极，双栅极或三栅极鳍FET器件。还公开了包括这种鳍式FET器件的电子系统。

4. 发明申请

US20110057269A1 SEMICONDUCTOR STRUCTURES INCLUDING DUAL FINS 有权
标题翻译：包括双FINS的半导体结构
公开(公告)号：US20110057269A1
公开(公告)日：2011-03-10
申请号：US12944529
申请日：2010-11-11
申请人： Aaron R. Wilson , Larson Lindholm , David Hwang
发明人： Aaron R. Wilson , Larson Lindholm , David Hwang
IPC分类号： H01L27/088
CPC分类号： H01L21/76224 , H01L29/66795 , H01L29/7853
摘要： Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by thinning shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of the substrate between the pair of STI structures, and recessing the STI structures so that the resulting dual fin structure protrudes from an active surface of the substrate. The dual fin structure may be used to form single-gate, double-gate or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.
摘要翻译： Fin-FET（鳍场效应晶体管）器件及其制造方法。 Fin-FET器件包括双鳍结构，其可以在源极区域和漏极区域之间形成沟道区域。在一些实施例中，通过使用一对浅沟槽隔离（STI）结构作为掩模来减薄浅沟槽隔离结构来形成双鳍结构，以在该一对STI结构之间限定衬底的一部分中的凹陷，以及凹陷 STI结构使得所得到的双翅片结构从基板的有效表面突出。双鳍结构可用于形成单栅极，双栅极或三栅极鳍FET器件。还公开了包括这种鳍式FET器件的电子系统。

5. 发明授权

US08497530B2 Semiconductor structures including dual fins 有权
标题翻译：半导体结构包括双鳍
公开(公告)号：US08497530B2
公开(公告)日：2013-07-30
申请号：US13424234
申请日：2012-03-19
申请人： Aaron R. Wilson , Larson Lindholm , David Hwang
发明人： Aaron R. Wilson , Larson Lindholm , David Hwang
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L29/66795 , H01L29/7853
摘要： Fin-FET (fin field-effect transistor) devices and methods of fabrication are disclosed. The fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of a substrate between the pair of STI structures, and recessing the pair of STI structures so that the resulting dual fin structures protrude from an active surface of the substrate. The dual fin structures may be used to form single-gate, double-gate, or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.
摘要翻译： Fin-FET（鳍场效应晶体管）器件和制造方法被公开。鳍式FET器件包括可在源极区域和漏极区域之间形成沟道区域的双鳍结构。在一些实施例中，通过形成浅沟槽隔离结构，使用一对浅沟槽隔离（STI）结构作为掩模来形成双鳍结构，以在一对STI结构之间限定衬底的一部分中的凹部，以及凹陷所述一对STI结构使得所得到的双翅片结构从所述基板的有效表面突出。双鳍结构可用于形成单栅极，双栅极或三栅极鳍FET器件。还公开了包括这种鳍式FET器件的电子系统。

6. 发明申请

US20120175748A1 SEMICONDUCTOR STRUCTURES INCLUDING DUAL FINS AND METHODS OF FABRICATION 有权
标题翻译：半导体结构包括双重FINS和制造方法
公开(公告)号：US20120175748A1
公开(公告)日：2012-07-12
申请号：US13424234
申请日：2012-03-19
申请人： Aaron R. Wilson , Larson Lindholm , David Hwang
发明人： Aaron R. Wilson , Larson Lindholm , David Hwang
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/76224 , H01L29/66795 , H01L29/7853
摘要： Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of the substrate between the pair of STI structures, and recessing the pair of STI structures so that the resulting dual fin structure protrudes from an active surface of the substrate. The dual fin structure may be used to form single-gate, double-gate, or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.
摘要翻译： Fin-FET（鳍场效应晶体管）器件及其制造方法。 Fin-FET器件包括双鳍结构，其可以在源极区域和漏极区域之间形成沟道区域。在一些实施例中，通过形成浅沟槽隔离结构，使用一对浅沟槽隔离（STI）结构作为掩模来形成双鳍结构，以在所述一对STI结构之间的衬底的一部分中限定凹陷，以及凹陷所述一对STI结构使得所得到的双翅片结构从所述基板的有源表面突出。双鳍结构可用于形成单栅极，双栅极或三栅极鳍FET器件。还公开了包括这种鳍式FET器件的电子系统。

7. 发明申请

US20080169504A1 Semiconductor constructions, methods of forming semiconductor constructions, and methods of recessing materials within openings 有权
标题翻译：半导体结构，形成半导体结构的方法以及在开口内凹陷材料的方法
公开(公告)号：US20080169504A1
公开(公告)日：2008-07-17
申请号：US11652863
申请日：2007-01-12
申请人： Larson Lindholm , Aaron R. Wilson , David K. Hwang
发明人： Larson Lindholm , Aaron R. Wilson , David K. Hwang
IPC分类号： H01L27/00 , H01L21/302 , H01L21/8236 , H01L21/8242
CPC分类号： H01L27/10891 , H01L21/31116 , H01L21/823412 , H01L21/823456 , H01L21/823807 , H01L21/823821 , H01L21/82385 , H01L27/10876 , H01L27/10879 , H01L29/4236 , H01L29/66795 , H01L29/7851 , H01L29/7854
摘要： Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C4F6 and C4F8. The recessed materials may be within isolation regions, and the recessing may be utilized to form trenches for receiving gatelines. Some embodiments include structures having an island of semiconductor material laterally surrounded by electrically insulative material. Two gatelines extend across the insulative material and across the island of semiconductor material. One of the gatelines is recessed deeper into the electrically insulative material than the other.
摘要翻译：一些实施方案包括使用包含C 4 N 6 F 6和C 4 F 8的蚀刻剂将多种材料凹入共同深度的方法， SUB>。凹陷的材料可以在隔离区域内，并且凹陷可以用于形成用于接收基准线的沟槽。一些实施例包括具有由电绝缘材料横向包围的半导体材料岛的结构。两种栅极延伸穿过绝缘材料和半导体材料岛。电绝缘材料中的一种比另一种更凹陷。

8. 发明申请

US20100072557A1 Semiconductor Constructions 有权
标题翻译：半导体建筑
公开(公告)号：US20100072557A1
公开(公告)日：2010-03-25
申请号：US12628910
申请日：2009-12-01
申请人： Larson Lindholm , Aaron R. Wilson , David K. Hwang
发明人： Larson Lindholm , Aaron R. Wilson , David K. Hwang
IPC分类号： H01L27/092
CPC分类号： H01L27/10891 , H01L21/31116 , H01L21/823412 , H01L21/823456 , H01L21/823807 , H01L21/823821 , H01L21/82385 , H01L27/10876 , H01L27/10879 , H01L29/4236 , H01L29/66795 , H01L29/7851 , H01L29/7854
摘要： Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C4F6 and C4F3. The recessed materials may be within isolation regions, and the recessing may be utilized to form trenches for receiving gatelines. Some embodiments include structures having an island of semiconductor material laterally surrounded by electrically insulative material. Two gatelines extend across the insulative material and across the island of semiconductor material. One of the gatelines is recessed deeper into the electrically insulative material than the other.
摘要翻译：一些实施方案包括使用包含C 4 F 6和C 4 F 3的蚀刻剂将多种材料凹入共同深度的方法。凹陷的材料可以在隔离区域内，并且凹陷可以用于形成用于接收基准线的沟槽。一些实施例包括具有由电绝缘材料横向包围的半导体材料岛的结构。两种栅极延伸穿过绝缘材料和半导体材料岛。电绝缘材料中的一种比另一种更凹陷。

9. 发明授权

US07948030B2 Semiconductor constructions of memory devices with different sizes of GateLine trenches 有权
标题翻译：具有不同尺寸的GateLine沟槽的存储器件的半导体结构
公开(公告)号：US07948030B2
公开(公告)日：2011-05-24
申请号：US12875828
申请日：2010-09-03
申请人： Larson Lindholm , Aaron R. Wilson , David K. Hwang
发明人： Larson Lindholm , Aaron R. Wilson , David K. Hwang
IPC分类号： H01L29/76
CPC分类号： H01L27/10891 , H01L21/31116 , H01L21/823412 , H01L21/823456 , H01L21/823807 , H01L21/823821 , H01L21/82385 , H01L27/10876 , H01L27/10879 , H01L29/4236 , H01L29/66795 , H01L29/7851 , H01L29/7854
摘要： Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C4F6 and C4F3. The recessed materials may be within isolation regions, and the recessing may be utilized to form trenches for receiving gatelines. Some embodiments include structures having an island of semiconductor material laterally surrounded by electrically insulative material. Two gatelines extend across the insulative material and across the island of semiconductor material. One of the gatelines is recessed deeper into the electrically insulative material than the other.
摘要翻译：一些实施方案包括使用包含C 4 F 6和C 4 F 3的蚀刻剂将多种材料凹入共同深度的方法。凹陷的材料可以在隔离区域内，并且凹陷可以用于形成用于接收基准线的沟槽。一些实施例包括具有由电绝缘材料横向包围的半导体材料岛的结构。两种栅极延伸穿过绝缘材料和半导体材料岛。电绝缘材料中的一种比另一种更凹陷。

10. 发明授权

US07808041B2 Semiconductor constructions of memory device with different depth gate line trenches 有权
标题翻译：具有不同深度栅极线沟槽的存储器件的半导体结构
公开(公告)号：US07808041B2
公开(公告)日：2010-10-05
申请号：US12628910
申请日：2009-12-01
申请人： Larson Lindholm , Aaron R. Wilson , David K. Hwang
发明人： Larson Lindholm , Aaron R. Wilson , David K. Hwang
IPC分类号： H01L29/76
CPC分类号： H01L27/10891 , H01L21/31116 , H01L21/823412 , H01L21/823456 , H01L21/823807 , H01L21/823821 , H01L21/82385 , H01L27/10876 , H01L27/10879 , H01L29/4236 , H01L29/66795 , H01L29/7851 , H01L29/7854
摘要： Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C4F6 and C4F8. The recessed materials may be within isolation regions, and the recessing may be utilized to form trenches for receiving gatelines. Some embodiments include structures having an island of semiconductor material laterally surrounded by electrically insulative material. Two gatelines extend across the insulative material and across the island of semiconductor material. One of the gatelines is recessed deeper into the electrically insulative material than the other.
摘要翻译：一些实施方案包括使用包含C 4 F 6和C 4 F 8的蚀刻剂将多种材料凹陷到共同深度的方法。凹陷的材料可以在隔离区域内，并且凹陷可以用于形成用于接收基准线的沟槽。一些实施例包括具有由电绝缘材料横向包围的半导体材料岛的结构。两种栅极延伸穿过绝缘材料和半导体材料岛。电绝缘材料中的一种比另一种更凹陷。

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