专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US11501679B2 Driving circuit with multiple stage registers performing voltage regulation 有权
公开(公告)号：US11501679B2
公开(公告)日：2022-11-15
申请号：US17523149
申请日：2021-11-10
申请人： AU Optronics Corporation
发明人： Wei-Li Lin , Che-Wei Tung
IPC分类号： G09G3/20
摘要： A driving circuit includes an S stage register, a first connect line, an (S+A) stage register and a second connect line. The S stage register receives an S stage control signal through a first switch unit and a second switch unit, so that the S stage register performs voltage regulation and outputs an S stage scan signal. The first connect line is electrically connected to the first switch unit of the S stage register. A third switch unit of the (S+A) stage register is electrically connected to the first connect line and a fourth switch unit of the (S+A) stage register for receiving the S stage scan signal, so that The (S+A) stage register performs voltage regulation. The second connect line is electrically connected to the second switch unit of the S stage register and the fourth switch unit of the (S+A) stage register.

2. 发明授权

US11361701B1 Driving circuit and driving method 有权
公开(公告)号：US11361701B1
公开(公告)日：2022-06-14
申请号：US17511157
申请日：2021-10-26
申请人： AU Optronics Corporation
发明人： Che-Wei Tung , Shang-Jie Wu , Yu-Chieh Kuo , Yu-Hsun Chiu , Che-Chia Chang , Yu-Zuo Lin , Chen-Ying Chou , Yi-Fan Chen
IPC分类号： G09G3/20 , H03K5/156 , H03K17/687
摘要： The present disclosure relates to a driving circuit including a pulse amplitude modulation (PAM) circuit and a pulse width modulation (PWM) circuit. The PAM circuit includes a first transistor, a first capacitor, and a second transistor. The PWM circuit includes a second capacitor, a third transistor, and a fourth transistor. The first capacitor's first terminal is connected to the first transistor's gate. The second transistor's first terminal is connected to the first capacitor's first terminal, and the second transistor's second terminal is connected to the first transistor's second terminal. The third transistor's gate is connected to the second capacitor's second terminal. The fourth transistor's first terminal is connected to the third transistor's gate, the fourth transistor's second terminal is connected to the third transistor's second terminal, and the fourth transistor's gate is connected to the second transistor's gate and configured to receive a first control signal.

3. 发明授权

US09377994B2 Gate driver circuit 有权
标题翻译：门驱动电路
公开(公告)号：US09377994B2
公开(公告)日：2016-06-28
申请号：US14225962
申请日：2014-03-26
申请人： AU Optronics Corporation
发明人： Wei-Li Lin , Che-Wei Tung , Chia-Heng Chen , Shu-Fang Hou
IPC分类号： G11C19/28 , G06F5/08
CPC分类号： G06F5/08
摘要： A gate driver circuit includes several shift register stages. One of shifter register stages includes a pull-up unit, a pull-up control unit, and an output unit. The pull-up unit is configured for generating a driving signal according to a first clock signal and an operating signal. The pull-up control unit is configured for generating a next-stage operating signal to a next-stage shift register stage according to the first clock signal, the operating signal and the driving signal. The output unit is configured for receiving the driving signal and generating a first gate driving signal and a second gate driving signal according to a first controlling signal and a second controlling signal, respectively.
摘要翻译：栅极驱动器电路包括多个移位寄存器级。移位寄存器级之一包括上拉单元，上拉控制单元和输出单元。上拉单元被配置为根据第一时钟信号和操作信号产生驱动信号。上拉控制单元被配置为根据第一时钟信号，操作信号和驱动信号产生到下一级移位寄存器级的下一级操作信号。输出单元被配置为分别接收驱动信号并根据第一控制信号和第二控制信号产生第一栅极驱动信号和第二栅极驱动信号。

4. 发明申请

US20140063398A1 DISPLAY PANEL AND REPAIRING METHOD THEREOF 审中-公开
标题翻译：显示面板及其修复方法
公开(公告)号：US20140063398A1
公开(公告)日：2014-03-06
申请号：US13831927
申请日：2013-03-15
申请人： AU OPTRONICS CORPORATION
发明人： Chun-Huan Chang , Chun-Hsin Liu , Kun-Yueh Lin , Ya-Ting Lin , Shu-Fang Hou , Che-Wei Tung , Wei-Li Lin
IPC分类号： G02F1/1362
CPC分类号： G02F1/136259 , G02F2001/136263 , G02F2001/136272
摘要： A display panel is provided. A substrate includes a non-display area and a display area including a center area, a first area, and a second area. First data lines are disposed in the first area and electrically connected to the first source driving circuit. Second data lines are disposed in the second area and electrically connected to the second source driving circuit. At least one first repairing line is electrically connected to the first source driving circuit, passes through the center area of the display area and overlaps with the first data lines, wherein the first repairing line is electrically insulated from the first data lines. At least one second repairing line is electrically connected to the second source driving circuit, passes through the center area of the display area and overlaps with the second data lines, wherein the second repairing line is electrically insulated from the second data lines.
摘要翻译：提供显示面板。基板包括非显示区域和包括中心区域，第一区域和第二区域的显示区域。第一数据线设置在第一区域中并电连接到第一源极驱动电路。第二数据线设置在第二区域中并电连接到第二源极驱动电路。至少一个第一修复线路电连接到第一源极驱动电路，穿过显示区域的中心区域并与第一数据线重叠，其中第一修复线路与第一数据线电绝缘。至少一个第二修复线路电连接到第二源极驱动电路，穿过显示区域的中心区域并与第二数据线重叠，其中第二修复线路与第二数据线电绝缘。

5. 发明授权

US11475813B2 Display panel and scan driver circuit thereof suitable for narrow border application 有权
公开(公告)号：US11475813B2
公开(公告)日：2022-10-18
申请号：US17067795
申请日：2020-10-12
申请人： AU Optronics Corporation
发明人： Che-Wei Tung , Wei-Li Lin , Yu-Zuo Lin , Chia-Ming Chang
IPC分类号： G09G5/00 , G09G3/20 , G11C19/28
摘要： A scan driver circuit including shift register units and gate control circuits is provided. The shift register units are in a peripheral area of a display panel, and for receiving first clock signals. The gate control circuits are in an active area of the display panel, and for receiving second clock signals. Each shift register unit is coupled with corresponding N of the gate control circuits, and for providing a corresponding one of the first clock signals as a control signal to the corresponding N of the gate control circuits. The corresponding N of the gate control circuits are coupled with corresponding M of gate lines. The corresponding N of the gate control circuits are for providing, according to the control signal, corresponding M of the second clock signals as M gate signals to the corresponding M of gate lines, in which M and N are positive integers.

6. 发明授权

US11443709B2 Display panel with reduced border area improving charging and discharging capacities of gate driving circuit 有权
公开(公告)号：US11443709B2
公开(公告)日：2022-09-13
申请号：US17394382
申请日：2021-08-04
申请人： Au Optronics Corporation
发明人： Che-Wei Tung , Wei-Li Lin , Chin-Hsien Chou , Yen-Wei Yeh
IPC分类号： G09G3/36
摘要： A display panel is provided. The display panel includes a plurality of scan lines and a gate driving circuit. The scan lines are disposed on the display panel along a first direction, and respectively provide a plurality of gate driving signals. The gate driving circuit is disposed on a first side of the display panel along a second direction. The second direction intersects the first direction. The gate driving circuit includes a plurality of bias generators and a plurality of signal output circuits. The signal output circuits are divided into a plurality of groups. The bias generators respectively correspond to the groups. The bias generators generate a plurality of first bias voltages. The groups generate the gate driving signals respectively according to the first bias voltages.

7. 发明授权

US10784288B2 Display panel having a grading wiring design 有权
公开(公告)号：US10784288B2
公开(公告)日：2020-09-22
申请号：US16192827
申请日：2018-11-16
申请人： Au Optronics Corporation
发明人： Che-Wei Tung , Wei-Li Lin , Keng-Chuan Cheng
IPC分类号： H01L27/12 , H01L23/52 , H01L23/528 , H01L25/18
摘要： A display panel has a display region, an external circuit region located at an edge of the display panel, and a first and second wiring regions. The first wiring region is located between the second wiring region and the external circuit region. The display panel includes a pixel array, gate driving circuit groups disposed between the second wiring region and the display region, first signal line groups extended from the external circuit region to the first and second wiring region, and second signal line groups extended from the second wiring region and connected to the corresponding gate driving circuit groups. In the second wiring region, a first portion of the first signal line groups overlapped with the second signal line groups has a first width, and a second portion thereof not overlapped with the second signal line groups has a third width which is larger than the first width.

8. 发明申请

US20220215809A1 DISPLAY PANEL 有权
公开(公告)号：US20220215809A1
公开(公告)日：2022-07-07
申请号：US17394382
申请日：2021-08-04
申请人： Au Optronics Corporation
发明人： Che-Wei Tung , Wei-Li Lin , Chin-Hsien Chou , Yen-Wei Yeh
IPC分类号： G09G3/36
摘要： A display panel is provided. The display panel includes a plurality of scan lines and a gate driving circuit. The scan lines are disposed on the display panel along a first direction, and respectively provide a plurality of gate driving signals. The gate driving circuit is disposed on a first side of the display panel along a second direction. The second direction intersects the first direction. The gate driving circuit includes a plurality of bias generators and a plurality of signal output circuits. The signal output circuits are divided into a plurality of groups. The bias generators respectively correspond to the groups. The bias generators generate a plurality of first bias voltages. The groups generate the gate driving signals respectively according to the first bias voltages.

9. 发明授权

US11250754B2 Driving circuit with multiple stage registers performing voltage regulation 有权
公开(公告)号：US11250754B2
公开(公告)日：2022-02-15
申请号：US16941624
申请日：2020-07-29
申请人： AU Optronics Corporation
发明人： Wei-Li Lin , Che-Wei Tung
IPC分类号： G09G3/20
摘要： A driving circuit includes a S stage register, a first connect line, a (S+A) stage register and a second connect line. The S stage register receives a S stage control signal through a first switch unit and a second switch unit, so that the S stage register performs voltage regulation and outputs a S stage scan signal. The first connect line is electrically connected to the first switch unit of the S stage register. A third switch unit of the (S+A) stage register is electrically connected to the first connect line and a fourth switch unit of the (S+A) stage register for receiving the S stage scan signal, so that The (S+A) stage register performs voltage regulation. The second connect line is electrically connected to the second switch unit of the S stage register and the fourth switch unit of the (S+A) stage register.

10. 发明申请

US20190393246A1 DISPLAY PANEL 审中-公开
公开(公告)号：US20190393246A1
公开(公告)日：2019-12-26
申请号：US16192827
申请日：2018-11-16
申请人： Au Optronics Corporation
发明人： Che-Wei Tung , Wei-Li Lin , Keng-Chuan Cheng
IPC分类号： H01L27/12 , H01L25/18 , H01L23/528
摘要： A display panel has a display region, an external circuit region located at an edge of the display panel, and a first and second wiring regions. The first wiring region is located between the second wiring region and the external circuit region. The display panel includes a pixel array, gate driving circuit groups disposed between the second wiring region and the display region, first signal line groups extended from the external circuit region to the first and second wiring region, and second signal line groups extended from the second wiring region and connected to the corresponding gate driving circuit groups. In the second wiring region, a first portion of the first signal line groups overlapped with the second signal line groups has a first width, and a second portion thereof not overlapped with the second signal line groups has a third width which is larger than the first width.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式