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1. 发明授权

US10521232B2 Data processing apparatus and method for processing a SIMD instruction specifying a control value having a first portion identifying a selected data size and a second portion identifying at least one control parameter having a number of bits that varies in dependence on a number of bits comprised by the first portion 有权
公开(公告)号：US10521232B2
公开(公告)日：2019-12-31
申请号：US15431955
申请日：2017-02-14
申请人： ARM Limited
发明人： David James Seal , Richard Roy Grisenthwaite , Nigel John Stephens
IPC分类号： G06F9/30 , G06F9/38 , G06F7/76
摘要： A data processing apparatus comprises a processing circuit and instruction decoder. A bitfield manipulation instruction controls the processing apparatus to generate at least one result data element from corresponding first and second source data elements. Each result data element includes a portion corresponding to a bitfield of the corresponding first source data element. Bits of the result data element that are more significant than the inserted bitfield have a prefix value that is selected, based on a control value specified by the instruction, as one of a first prefix value having a zero value, a second prefix value having the value of a portion of the corresponding second source data element, and a third prefix value corresponding to a sign extension of the bitfield of the first source data element.

2. 发明申请

US20150186142A1 MIXED SIZE DATA PROCESSING OPERATION 审中-公开
标题翻译：混合尺寸数据处理操作
公开(公告)号：US20150186142A1
公开(公告)日：2015-07-02
申请号：US14659662
申请日：2015-03-17
申请人： ARM Limited
发明人： Nigel John Stephens , David James Seal
IPC分类号： G06F9/30
CPC分类号： G06F9/30149 , G06F9/30043 , G06F9/30098 , G06F9/3016 , G06F9/30192 , G06F9/345 , G06F9/355
摘要： A data processing system includes a processor core and a memory. The processor core includes processing circuitry controlled by control signals generated by decoder circuitry which decodes program instructions. The program instructions include mixed operand size instructions (either load/store instructions or arithmetic instructions) which have a first input operand of a first operand size and a second input operand of a second input operand size where the second operand size is smaller than the first operand size. The processing performed first converts the second operand so as to have the first operand size. The processing then generates a third operand using as inputs the first operand of the first operand size and the second operand now converted to have the first operand size.
摘要翻译：数据处理系统包括处理器核和存储器。处理器核心包括由解码器电路产生的控制信号控制的处理电路，其解码程序指令。程序指令包括具有第一操作数大小的第一输入操作数和第二输入操作数大小的第二输入操作数的混合操作数大小指令（加载/存储指令或算术指令），其中第二操作数大小小于第一操作数大小操作数大小。所执行的处理首先将第二操作数转换为具有第一操作数大小。然后，处理使用第一操作数大小的第一操作数作为输入并且现在转换为具有第一操作数大小的第二操作数作为输入产生第三操作数。

3. 发明申请

US20150106585A1 ADDRESS GENERATION IN A DATA PROCESSING APPARATUS 有权
标题翻译：数据处理设备中的地址生成
公开(公告)号：US20150106585A1
公开(公告)日：2015-04-16
申请号：US14573193
申请日：2014-12-17
申请人： ARM Limited
发明人： Nigel John Stephens , David James Seal
IPC分类号： G06F9/355 , G06F12/10
CPC分类号： G06F9/3557 , G06F9/30007 , G06F9/30112 , G06F9/30167 , G06F9/342 , G06F9/345 , G06F2212/657
摘要： A data processing apparatus is provided comprising processing circuitry and an instruction decoder responsive to program instructions to control processing circuitry to perform the data processing. The instruction decoder is responsive to an address calculating instruction to perform an address calculating operation for calculating a partial address result from a non-fixed reference address and a partial offset value such that a full address specifying a memory location of an information entity is calculable from said partial address result using at least one supplementary program instruction. The partial offset value has a bit-width greater than or equal to said instruction size and is encoded within at least one partial offset field of said address calculating instruction. A corresponding data processing method, virtual machine and computer program product are also provided.
摘要翻译：提供了一种数据处理装置，其包括响应于程序指令的处理电路和指令解码器，以控制处理电路执行数据处理。指令解码器响应于地址计算指令来执行地址计算操作，用于从非固定参考地址和部分偏移值计算部分地址结果，使得可以从...计算指定信息实体的存储位置的完整地址所述部分地址结果使用至少一个补充程序指令。部分偏移值具有大于或等于所述指令大小的位宽，并且被编码在所述地址计算指令的至少一个部分偏移字段内。还提供了相应的数据处理方法，虚拟机和计算机程序产品。

4. 发明授权

US09619225B2 Apparatus and method including an instruction for performing a logical operation on a repeating data value generated based on data size and control parameter portions specified by the instruction 有权
公开(公告)号：US09619225B2
公开(公告)日：2017-04-11
申请号：US14878188
申请日：2015-10-08
申请人： ARM Limited
发明人： David James Seal , Richard Roy Grisenthwaite , Nigel John Stephens
IPC分类号： G06F9/30 , G06F9/305 , G06F7/76
CPC分类号： G06F9/3016 , G06F7/764 , G06F7/768 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/30145 , G06F9/3887
摘要： A data processing apparatus comprises a processing circuit and instruction decoder. A bitfield manipulation instruction controls the processing apparatus to generate at least one result data element from corresponding first and second source data elements. Each result data element includes a portion corresponding to a bitfield of the corresponding first source data element. Bits of the result data element that are more significant than the inserted bitfield have a prefix value that is selected, based on a control value specified by the instruction, as one of a first prefix value having a zero value, a second prefix value having the value of a portion of the corresponding second source data element, and a third prefix value corresponding to a sign extension of the bitfield of the first source data element. Bitwise logical instructions are also described.

5. 发明授权

US09495163B2 Address generation in a data processing apparatus 有权
公开(公告)号：US09495163B2
公开(公告)日：2016-11-15
申请号：US14573193
申请日：2014-12-17
申请人： ARM Limited
发明人： Nigel John Stephens , David James Seal
IPC分类号： G06F9/355 , G06F9/345 , G06F9/30 , G06F9/34 , G06F12/10
CPC分类号： G06F9/3557 , G06F9/30007 , G06F9/30112 , G06F9/30167 , G06F9/342 , G06F9/345 , G06F2212/657
摘要： A data processing apparatus is provided comprising processing circuitry and an instruction decoder responsive to program instructions to control processing circuitry to perform the data processing. The instruction decoder is responsive to an address calculating instruction to perform an address calculating operation for calculating a partial address result from a non-fixed reference address and a partial offset value such that a full address specifying a memory location of an information entity is calculable from said partial address result using at least one supplementary program instruction. The partial offset value has a bit-width greater than or equal to said instruction size and is encoded within at least one partial offset field of said address calculating instruction. A corresponding data processing method, virtual machine and computer program product are also provided.

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