专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20210342248A1 AN APPARATUS AND METHOD FOR MONITORING EVENTS IN A DATA PROCESSING SYSTEM 有权
公开(公告)号：US20210342248A1
公开(公告)日：2021-11-04
申请号：US17271399
申请日：2019-08-30
申请人： Arm Limited
发明人： Timothy HAYES , Giacomo GABRIELLI , Matthew James HORSNELL
IPC分类号： G06F11/34 , G06F11/30
摘要： An apparatus and method are provided for monitoring events in a data processing system. The apparatus has first event monitoring circuitry for monitoring occurrences of a first event within a data processing system, and for asserting a first signal to indicate every m-th occurrence of the first event, where m is an integer of 1 or more. In addition second event monitoring circuitry is used to monitor occurrences of a second event within the data processing system, and to assert a second signal to indicate every n-th occurrence of the second event, where n is an integer of 1 or more. History maintenance circuitry then maintains event history information which is updated in dependence on the asserted first and second signals. Further, history analysis circuitry is responsive to an analysis trigger to analyse the event history information in order to detect a reporting condition when the event history information indicates that a ratio between occurrences of the first event and the occurrences of the second event is outside an acceptable range. The history analysis circuitry is then responsive to detection of the reporting condition to assert a report signal. This provides a particularly efficient and effective mechanism for monitoring ratios of events within a data processing system.

2. 发明申请

US20190258489A1 HANDLING OF INTER-ELEMENT ADDRESS HAZARDS FOR VECTOR INSTRUCTIONS 审中-公开
公开(公告)号：US20190258489A1
公开(公告)日：2019-08-22
申请号：US16331179
申请日：2017-08-14
申请人： ARM LIMITED
发明人： Matthew James HORSNELL , Mbou EYOLE
IPC分类号： G06F9/38 , G06F9/30 , G06F9/54
摘要： An apparatus has processing circuitry supporting vector load and store instructions. In response to a transaction start event, the processing circuitry executes one or more subsequent instructions speculatively. In response to a transaction end event, the processing circuitry commits speculative results of those instructions. Hazard detection circuitry detects whether an inter-element address hazard occurs between an address for data element J for an earlier vector load instruction and an address for data element K for a later vector store instruction, where K and J are not equal. In response to detecting the inter-element address hazard, the hazard detection circuitry triggers the processing circuitry to abort further processing of the instructions following the transaction start event and to prevent the speculative results being committed. This approach can provide faster performance for vectorised code.

3. 发明申请

US20130132737A1 CRYPTOGRAPHIC SUPPORT INSTRUCTIONS 有权
公开(公告)号：US20130132737A1
公开(公告)日：2013-05-23
申请号：US13627209
申请日：2012-09-26
申请人： ARM LIMITED
发明人： Matthew James HORSNELL , Richard Roy GRISENTHWAITE , Daniel KERSHAW , Stuart David BILES
IPC分类号： G06F9/30 , G06F21/60
CPC分类号： G06F21/602 , G06F9/30007 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30145 , G06F9/3887 , G09C1/00 , H04L9/0643 , H04L9/3239 , H04L2209/12 , H04L2209/125
摘要： A data processing system 2 includes a single instruction multiple data register file 12 and single instruction multiple processing circuitry 14. The single instruction multiple data processing circuitry 14 supports execution of cryptographic processing instructions for performing parts of a hash algorithm. The operands are stored within the single instruction multiple data register file 12. The cryptographic support instructions do not follow normal lane-based processing and generate output operands in which the different portions of the output operand depend upon multiple different elements within the input operand.

4. 发明申请

US20200278882A1 PERMITTING UNABORTED PROCESSING OF TRANSACTION AFTER EXCEPTION MASK UPDATE INSTRUCTION 审中-公开
公开(公告)号：US20200278882A1
公开(公告)日：2020-09-03
申请号：US16651017
申请日：2018-08-21
申请人： Arm Limited
发明人： Matthew James HORSNELL , Grigorios MAGKLIS , Richard Roy GRISENTHWAITE , Stephan DIESTELHORST
IPC分类号： G06F9/46 , G06F9/30 , G06F9/38 , G06F9/48 , G06F11/14
摘要： A data processing apparatus has processing circuitry with transactional memory support circuitry to support execution of a transaction using transactional memory. In response to an exception mask updating instruction which updates exception mask information to enable at least one subset of exceptions which was disabled at the start of processing of a transaction, the processing circuitry permits un-aborted processing of one or more subsequent instruction of the transaction that follow the exception mask update instruction.

5. 发明申请

US20170161112A1 DYNAMIC SAVING OF REGISTERS IN TRANSACTIONS 审中-公开
公开(公告)号：US20170161112A1
公开(公告)日：2017-06-08
申请号：US15324082
申请日：2015-06-11
申请人： ARM LIMITED
发明人： Matthew James HORSNELL , Stephan DIESTELHORST
IPC分类号： G06F9/50
摘要： A data processing apparatus comprises a plurality of data storage elements, each configured to store data. Mask storage circuitry stores a mask and processing circuitry executes one or more instructions. A data saver is configured, in response to a transactional start instruction, to select a subset of the data storage elements and to save a backup of the subset of the data storage elements. Mask control circuitry then updates the mask to indicate the subset of the data storage elements selected by the data saver. Finally, a monitor detects write or write attempts made to one of the data storage elements not indicated by the mask. Accordingly, a user need not save all data storage elements (e.g. registers) in a system or specify precisely which data storage elements must be saved in order to perform a transaction. Instead, the set of data storage elements that must be saved can be determined and specified dynamically, and the system can respond if an attempt is made to write to a data storage element that has not been saved or backed up.

6. 发明申请

US20170161095A1 CALL STACK MAINTENANCE FOR A TRANSACTIONAL DATA PROCESSING EXECUTION MODE 有权
公开(公告)号：US20170161095A1
公开(公告)日：2017-06-08
申请号：US15325301
申请日：2015-06-09
申请人： ARM LIMITED
发明人： Matthew James HORSNELL , Stephan DIESTELHORST
IPC分类号： G06F9/46 , G06F12/128 , G06F12/0891 , G06F12/0875
CPC分类号： G06F9/467 , G06F9/528 , G06F12/0811 , G06F12/0875 , G06F12/0891 , G06F12/128 , G06F2212/1032 , G06F2212/451 , G06F2212/621
摘要： A data processing apparatus and method of data processing are provided, which relate to the operation of a processor which maintains a push call stack in dependence on the data processing instructions executed. The processor is configured to operate in a transactional execution mode when the data processing instructions seek access to a stored data item which is shared with a further processor. When the processor enters its transactional execution mode it stores a copy of the current stack depth indication and thereafter, when operating in its transactional execution mode, further modifications to the call stack are compared to the copy of the stack depth indication stored. If the relative stacking position of the required modification is in a positive stack growth direction with respect to the copy stored, the modification to the call stack is labelled as non-speculative. Conversely if the modification to the call stack is to be made at a relative stacking position which is not in a positive growth direction with respect to the position indicated by the copy stored, then that modification is labelled as speculative. The size of the write-set associated with maintaining the call stack whilst in transactional execution mode can therefore be reduced.

7. 发明公开

US20230280904A1 MONITORING MEMORY LOCATIONS TO IDENTIFY WHETHER DATA STORED AT THE MEMORY LOCATIONS HAS BEEN MODIFIED 审中-公开
公开(公告)号：US20230280904A1
公开(公告)日：2023-09-07
申请号：US18040577
申请日：2021-08-05
申请人： Arm Limited
发明人： Matthew James HORSNELL
IPC分类号： G06F3/06 , G06F12/0815
CPC分类号： G06F3/061 , G06F3/0653 , G06F3/0673 , G06F12/0815
摘要： An apparatus comprises address storage circuitry to store indications of a first set of memory locations of a shared memory; a capacity indicator to indicate whether a capacity of the address storage circuitry has been reached, and monitoring circuitry to monitor the first set of memory locations and a second set of memory locations of the shared memory, identified in further storage circuitry to identify whether data stored at either set of memory locations has been modified. The monitoring circuitry is responsive to determining that the data has been modified to generate an indication that the data has been modified, and processing circuitry receives the indication and executes a monitor-address instruction specifying an address of a new memory location in the shared memory to update the address storage circuitry or the further storage circuitry to indicate the new address, depending on the capacity indicator.

8. 发明申请

US20210141643A1 TRANSACTIONAL COMPARE-AND-DISCARD INSTRUCTION 有权
公开(公告)号：US20210141643A1
公开(公告)日：2021-05-13
申请号：US17258287
申请日：2019-05-09
申请人： Arm Limited
发明人： Matthew James HORSNELL , Grigorios MAGKLIS , Stephan DIESTELHORST
IPC分类号： G06F9/30 , G06F9/38 , G06F13/16
摘要： An apparatus comprising: processing circuitry to process threads of data processing; and transactional memory support circuitry to support execution of a transaction within a thread processed by the processing circuitry. In response to a transactional compare-and-discard instruction executed within a given transaction, specifying a target address and a compare value, the processing circuitry loads a target data value from a memory location corresponding to the target address; sets at least one condition status indication depending on a result of comparing the target data value and the compare value; and discards the target data value without adding the target address to a working set of addresses tracked for the given transaction. This is useful for enabling thread level speculation to be implemented on a transactional memory architecture.

9. 发明申请

US20200167292A1 ADDRESS TRANSLATION DATA INVALIDATION 审中-公开
公开(公告)号：US20200167292A1
公开(公告)日：2020-05-28
申请号：US16625102
申请日：2018-06-01
申请人： ARM LIMITED
发明人： Matthew James HORSNELL , Grigorios MAGKLIS , Richard Roy GRISENTHWAITE
IPC分类号： G06F12/1027 , G06F9/54 , G06F9/46 , G06F12/0873
摘要： A data processing system (2) including one or more transaction buffers (16, 18, 20) storing address translation data executes translation buffer invalidation instructions TLBI within respective address translation contexts VMID, ASID, X. Translation buffer invalidation signals generated as a consequence of execution of the translation buffer invalidation instructions are broadcast to respective translation buffers and include signals which specify the address translation context of the translation buffer invalidation instruction that was executed. This address translation context specified within the translation buffer invalidation signals is used to gate whether or not those translation buffer invalidation signals when received by translation buffers which are potential targets for the invalidation are or are not flushed. The address translation context data provided within the translation buffer invalidation signals may also be used to control whether or not local memory transactions for a local transactional memory access are or are not aborted upon receipt of the translation buffer invalidation signals.

10. 发明申请

US20170351517A1 DEBUGGING DATA PROCESSING TRANSACTIONS 审中-公开
公开(公告)号：US20170351517A1
公开(公告)日：2017-12-07
申请号：US15538365
申请日：2015-11-23
申请人： ARM LIMITED
发明人： Stephan DIESTELHORST , Michael John WILLIAMS , Richard Roy GRISENTHWAITE , Matthew James HORSNELL
IPC分类号： G06F9/30 , G06F9/38 , G06F12/08 , G06F12/126
CPC分类号： G06F9/30043 , G06F9/3004 , G06F9/3834 , G06F9/3842 , G06F9/455 , G06F9/46 , G06F9/467 , G06F11/362 , G06F11/3636 , G06F12/08 , G06F12/126
摘要： A data processing system supporting execution of transactions comprising one or more program instructions that execute to generate speculative updates is provided. The speculative updates are committed in normal operation if the transaction completes without a conflict. Start of execution of a transaction may be detected and execution diverted to be performed by software emulation rather than direct execution by the processing hardware. The software emulation may store data representing one or more versions of the speculative updates generated during the emulation. The software emulation may also detect conflicts with the transaction being emulated. In order to facilitate modifying the behaviour of other parts of the system interacting with a transaction under investigation, a non-standard response signal may be returned in response to a detected memory access request to a transaction being emulated. The non-standard response signal may be used to initiate the request source to follow a subsequent path of processing different from that which it would otherwise follow. Support is also provided for detecting a trigger condition which results in the halting (freezing) of a partially completed transaction and the saving the speculative updates associated with that partially completed transaction to the architectural state of the system.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式