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1. 发明申请

US20150032794A1 END-TO-END FLOW CONTROL IN SYSTEM ON CHIP INTERCONNECTS 审中-公开
标题翻译：芯片互连系统端到端流控制
公开(公告)号：US20150032794A1
公开(公告)日：2015-01-29
申请号：US13953059
申请日：2013-07-29
申请人： APPLIED MICRO CIRCUITS CORPORATION
发明人： Millind Mittal , Phil Mitchell
IPC分类号： H04L12/819
CPC分类号： H04L47/215 , H04L47/2408
摘要： Provided is an end-to-end flow control management for a system on chip interface. As tokens are injected into agents arranged in a computer network, the input point for the token is dynamically changed such that tokens are not always injected into the same agent. Additionally or alternatively, as tokens are injected into a token ring, the tokens are initially not activated until a predetermined event occurs (e.g., after a specific number of hops). Additionally or alternatively, also provided is a free pool manager that can keep at least some high priority slots available by consuming lower priority slots first.
摘要翻译：提供了一种用于片上系统接口的端到端流控制管理。由于令牌被注入到安排在计算机网络中的代理中，令牌的输入点被动态地改变，使得令牌并不总是被注入同一个代理。附加地或替代地，当令牌被注入到令牌环中时，令牌最初不被激活，直到发生预定事件（例如，在特定数量的跳数之后）。附加地或替代地，还提供了一个空闲池管理器，其可以首先通过消耗较低优先级时隙来保持至少一些高优先级时隙可用。

2. 发明授权

US09720830B2 Systems and methods facilitating reduced latency via stashing in system on chips 有权
公开(公告)号：US09720830B2
公开(公告)日：2017-08-01
申请号：US14796167
申请日：2015-07-10
申请人： APPLIED MICRO CIRCUITS CORPORATION
发明人： Millind Mittal
IPC分类号： G06F12/00 , G06F12/0811 , G06F12/084 , G06F12/0842 , G06F12/0875
CPC分类号： G06F12/0811 , G06F12/084 , G06F12/0842 , G06F12/0875 , G06F2212/1024 , G06F2212/251 , G06F2212/452 , G06F2212/602
摘要： Systems and methods that facilitate reduced latency via stashing in multi-level cache memory architectures of systems on chips (SoCs) are provided. One method involves stashing, by a device includes a plurality of multi-processor central processing unit cores, first data into a first cache memory of a plurality of cache memories, the plurality of cache memories being associated with a multi-level cache memory architecture. The method also includes generating control information including: a first instruction to cause monitoring contents of a second cache memory of the plurality of cache memories to determine whether a defined condition is satisfied for the second cache memory; and a second instruction to cause prefetching the first data into the second cache memory of the plurality of cache memories based on a determination that the defined condition is satisfied.

3. 发明申请

US20160092379A1 PRIORITY FRAMEWORK FOR A COMPUTING DEVICE 有权
标题翻译：用于计算设备的优先级框架
公开(公告)号：US20160092379A1
公开(公告)日：2016-03-31
申请号：US14497619
申请日：2014-09-26
申请人： APPLIED MICRO CIRCUITS CORPORATION
发明人： Kjeld Svendsen , Millind Mittal , Gaurav Singh
IPC分类号： G06F13/18
CPC分类号： G06F13/18 , Y02D10/14
摘要： Proving for a framework for propagating priorities to a memory subsystem in a computing system environment is disclosed herein. By way of example, a memory access handler is provided for managing memory access requests and determining associated priorities. The memory access handler includes logic configured for propagating memory requests and the associated priorities to lower levels of a computer hierarchy. A memory subsystem receives the memory access requests and the priorities.
摘要翻译：本文公开了在计算系统环境中向存储器子系统传播优先权的框架。作为示例，提供存储器访问处理程序用于管理存储器访问请求并确定相关联的优先级。存储器访问处理器包括被配置为将存储器请求和相关联的优先级传播到较低级别的计算机层次结构的逻辑。存储器子系统接收存储器访问请求和优先级。

4. 发明授权

US09928183B2 Priority framework for a computing device 有权
公开(公告)号：US09928183B2
公开(公告)日：2018-03-27
申请号：US14497619
申请日：2014-09-26
申请人： APPLIED MICRO CIRCUITS CORPORATION
发明人： Kjeld Svendsen , Millind Mittal , Gaurav Singh
IPC分类号： G06F13/18
CPC分类号： G06F13/18 , Y02D10/14
摘要： Proving for a framework for propagating priorities to a memory subsystem in a computing system environment is disclosed herein. By way of example, a memory access handler is provided for managing memory access requests and determining associated priorities. The memory access handler includes logic configured for propagating memory requests and the associated priorities to lower levels of a computer hierarchy. A memory subsystem receives the memory access requests and the priorities.

5. 发明申请

US20170010966A1 SYSTEMS AND METHODS FACILITATING REDUCED LATENCY VIA STASHING IN SYSTEM ON CHIPS 有权
标题翻译：系统和方法通过在系统中的堆栈来实现减少的延迟
公开(公告)号：US20170010966A1
公开(公告)日：2017-01-12
申请号：US14796167
申请日：2015-07-10
申请人： APPLIED MICRO CIRCUITS CORPORATION
发明人： Millind Mittal
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/084 , G06F12/0842 , G06F12/0875 , G06F2212/1024 , G06F2212/251 , G06F2212/452 , G06F2212/602
摘要： Systems and methods that facilitate reduced latency via stashing in multi-level cache memory architectures of systems on chips (SoCs) are provided. One method involves stashing, by a device includes a plurality of multi-processor central processing unit cores, first data into a first cache memory of a plurality of cache memories, the plurality of cache memories being associated with a multi-level cache memory architecture. The method also includes generating control information including: a first instruction to cause monitoring contents of a second cache memory of the plurality of cache memories to determine whether a defined condition is satisfied for the second cache memory; and a second instruction to cause prefetching the first data into the second cache memory of the plurality of cache memories based on a determination that the defined condition is satisfied.
摘要翻译：提供了通过堆叠在片上系统（SoC）的多级高速缓存存储器体系结构中促进减少延迟的系统和方法。一种方法涉及通过设备包括多个多处理器中央处理单元核心的第一数据进入多个高速缓存存储器中的第一高速缓存存储器，所述多个高速缓冲存储器与多级高速缓冲存储器结构相关联。该方法还包括产生控制信息，该控制信息包括：第一指令，用于使多个高速缓存存储器中的第二高速缓存存储器的内容的监视，以确定对于第二高速缓冲存储器是否满足定义的条件; 以及第二指令，用于基于满足所定义的条件的确定，将所述第一数据预取到所述多个高速缓冲存储器的第二高速缓冲存储器中。

6. 发明申请

US20150324133A1 SYSTEMS AND METHODS FACILITATING MULTI-WORD ATOMIC OPERATION SUPPORT FOR SYSTEM ON CHIP ENVIRONMENTS 审中-公开
标题翻译：系统和方法，促进芯片环境系统的多重原理操作支持
公开(公告)号：US20150324133A1
公开(公告)日：2015-11-12
申请号：US14264716
申请日：2014-04-29
申请人： APPLIED MICRO CIRCUITS CORPORATION
发明人： Millind Mittal
IPC分类号： G06F3/06
CPC分类号： G06F9/3834 , G06F3/0613 , G06F3/0655 , G06F3/0671
摘要： Systems and methods that facilitate multi-word atomic operation support for systems on chip are described. One method involves: receiving an instruction associated with a calling process, and determining a first memory width associated with execution of the instruction based on an operator of the instruction and a width of at least one operand of the instruction. The instruction can be associated with an atomic operation. In some embodiments, the instruction contains a message having a first field identifying the operator and a second field identifying the operand.
摘要翻译：描述了促进片上系统的多字母原子操作支持的系统和方法。一种方法包括：接收与呼叫过程相关联的指令，以及基于所述指令的操作符和所述指令的至少一个操作数的宽度来确定与所述指令的执行相关联的第一存储器宽度。该指令可以与原子操作相关联。在一些实施例中，指令包含具有标识操作者的第一字段和标识操作数的第二字段的消息。

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