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1. 发明申请

US20180349044A1 Programming Schemes for Avoidance or Recovery from Cross-Temperature Read Failures 审中-公开
公开(公告)号：US20180349044A1
公开(公告)日：2018-12-06
申请号：US15716703
申请日：2017-09-27
申请人： Apple Inc.
发明人： Barak Baum , Barak Sagiv , Einav Yogev , Eyal Gurgi , Ariel Landau
IPC分类号： G06F3/06 , G06F11/10
CPC分类号： G06F3/0619 , G06F11/002 , G06F11/1048 , G06F11/1072 , G06F11/108 , G06F11/3058 , G11C7/04 , G11C11/5642
摘要： A memory system includes an interface and storage circuitry. The interface is configured to communicate with a plurality of memory cells that store data by setting the memory cells to analog voltages representative of respective storage values. The storage circuitry is configured to receive data for storage, to measure a temperature at a time of programming the received data, and, to program the received data to the memory cells using a first programming scheme when the measured temperature falls within a predefined normal temperature range, and otherwise to program the received data to the memory cells using a second programming scheme having a lower net storage utilization than the first programming scheme.

2. 发明申请

US20170255396A1 PARALLEL SCHEDULING OF WRITE COMMANDS TO MULTIPLE MEMORY DEVICES 有权
公开(公告)号：US20170255396A1
公开(公告)日：2017-09-07
申请号：US15057145
申请日：2016-03-01
申请人： Apple Inc.
发明人： Yoni Labenski , Roman Gindin , Etai Zaltsman , Moti Altahan , Yoram Harel , Barak Baum
IPC分类号： G06F3/06
CPC分类号： G06F3/0613 , G06F3/0647 , G06F3/0659 , G06F3/0683 , G06F3/0688
摘要： A controller includes an interface and a processor. The interface is configured to communicate with multiple memory devices over a link. The processor is configured to select at least first and second memory devices for writing, and to write at least first and second data units in sequence to the first memory device over the link, while avoiding writing to any of the other memory devices until transferal of the at least first and second data units over the link has been completed, to write at least one data unit to the second memory device after transferring the at least first and second data units to the first memory device, and, in response to verifying that the first memory device is ready to receive subsequent data, to write to the first memory device at least a third data unit.

3. 发明授权

US09697075B2 Efficient search for optimal read thresholds in flash memory 有权
公开(公告)号：US09697075B2
公开(公告)日：2017-07-04
申请号：US14847037
申请日：2015-09-08
申请人： Apple Inc.
发明人： Yonathan Tate , Barak Baum , Moti Teitel
IPC分类号： G11C16/04 , G11C29/00 , G06F11/10 , G11C7/14 , G11C11/56 , G11C16/28
CPC分类号： G06F11/1068 , G11C7/14 , G11C11/5642 , G11C16/28
摘要： A method includes storing data encoded with an ECC in a group of memory cells by writing respective storage values to the memory cells. Multiple sets of readout results are read from the memory cells by comparing the storage values to one or more threshold combinations, each including multiple read thresholds. A plurality of partial syndromes of the ECC is computed, each partial syndrome computed over the readout results that were read using a respective threshold combination. A respective syndrome is calculated for each threshold combination, in at least a subset of all possible threshold combinations, based on one or more of the partial syndromes associated with that threshold combination. A preferred threshold combination is selected, from among the threshold combinations, for which a weight of the respective syndrome is minimal, by processing less than all the partial syndromes associated with all the possible threshold combinations.

4. 发明申请

US20170068591A1 EFFICIENT SEARCH FOR OPTIMAL READ THRESHOLDS IN FLASH MEMORY 有权
标题翻译：有效的搜索闪存中的最佳读取阈值
公开(公告)号：US20170068591A1
公开(公告)日：2017-03-09
申请号：US14847037
申请日：2015-09-08
申请人： Apple Inc.
发明人： Yonathan Tate , Barak Baum , Moti Teitel
IPC分类号： G06F11/10 , G11C29/52 , G11C16/26 , G11C11/56 , G11C16/10
CPC分类号： G06F11/1068 , G11C7/14 , G11C11/5642 , G11C16/28
摘要： A method includes storing data encoded with an ECC in a group of memory cells by writing respective storage values to the memory cells. Multiple sets of readout results are read from the memory cells by comparing the storage values to one or more threshold combinations, each including multiple read thresholds. A plurality of partial syndromes of the ECC is computed, each partial syndrome computed over the readout results that were read using a respective threshold combination. A respective syndrome is calculated for each threshold combination, in at least a subset of all possible threshold combinations, based on one or more of the partial syndromes associated with that threshold combination. A preferred threshold combination is selected, from among the threshold combinations, for which a weight of the respective syndrome is minimal, by processing less than all the partial syndromes associated with all the possible threshold combinations.
摘要翻译：一种方法包括通过将相应的存储值写入存储器单元来将通过ECC编码的数据存储在一组存储器单元中。通过将存储值与一个或多个阈值组合进行比较，每组包括多个读取阈值，从存储器单元读取多组读出结果。计算出ECC的多个部分综合征，使用相应的阈值组合读取的读出结果计算每个部分校正子。基于与该阈值组合相关联的一个或多个部分综合征，在所有可能的阈值组合的至少一个子集中针对每个阈值组合计算相应的综合征。通过处理小于与所有可能的阈值组合相关联的所有部分综合征，从相应综合征的权重最小的阈值组合中选择优选阈值组合。

5. 发明申请

US20160189783A1 STORAGE IN CHARGE-TRAP MEMORY STRUCTURES USING ADDITIONAL ELECTRICALLY-CHARGED REGIONS 审中-公开
公开(公告)号：US20160189783A1
公开(公告)日：2016-06-30
申请号：US15066020
申请日：2016-03-10
申请人： Apple Inc.
发明人： Arik Rizel , Avraham Poza Meir , Yael Shur , Eyal Gurgi , Barak Baum
IPC分类号： G11C16/24 , G11C16/10 , G11C16/04
CPC分类号： G11C16/24 , G11C11/5671 , G11C16/0466 , G11C16/0475 , G11C16/10 , G11C16/26 , H01L27/11568 , H01L29/42328
摘要： A device includes a memory and a read/write (R/W) unit. The memory includes multiple gates coupled to a common charge-trap layer. The R/W unit is configured to program and read the memory by creating and reading a set of electrically-charged regions in the common charge-trap layer, wherein at least a given region in the set is not uniquely associated with any single one of the gates.

6. 发明申请

US20130297989A1 Memory Device Readout Using Multiple Sense Times 有权
标题翻译：使用多重检测时间的存储器件读数
公开(公告)号：US20130297989A1
公开(公告)日：2013-11-07
申请号：US13936622
申请日：2013-07-08
申请人： Apple Inc.
发明人： Avraham Poza Meir , Barak Baum , Naftali Sommer
IPC分类号： G06F11/10
CPC分类号： G06F11/1008 , G11C7/06 , G11C8/08 , G11C8/12 , G11C11/4091 , G11C11/5642 , G11C13/004 , G11C13/0061 , G11C16/26 , G11C16/349 , G11C27/005 , G11C29/00 , G11C29/021 , G11C29/028 , G11C2211/5641
摘要： A method for data storage includes storing data in a group of analog memory cells by writing respective storage values into the memory cells in the group. One or more of the memory cells in the group are read using a first readout operation that senses the memory cells with a first sense time. At least one of the memory cells in the group is read using a second readout operation that senses the memory cells with a second sense time, longer than the first sense time. The data stored in the group of memory cells is reconstructed based on readout results of the first and second readout operations.
摘要翻译：用于数据存储的方法包括通过将相应的存储值写入组中的存储器单元来将数据存储在一组模拟存储器单元中。使用以第一感测时间感测存储器单元的第一读出操作读取组中的一个或多个存储器单元。使用第二读出操作来读取组中的至少一个存储器单元，该第二读出操作以比第一感测时间长的第二感测时间感测存储器单元。基于第一和第二读出操作的读出结果重建存储在存储单元组中的数据。

7. 发明授权

US10332608B2 Memory block usage based on block location relative to array edge 有权
公开(公告)号：US10332608B2
公开(公告)日：2019-06-25
申请号：US15992229
申请日：2018-05-30
申请人： Apple Inc.
发明人： Yael Shur , Assaf Shappir , Barak Baum , Roman Guy , Michael Tsohar
IPC分类号： G11C16/34 , G11C16/10 , G11C16/08
摘要： A storage device includes storage circuitry and multiple memory blocks. The multiple memory blocks are arranged in an array, and each of the memory blocks includes multiple memory cells. A maximal number of programming cycles that a memory block of the multiple memory blocks sustains depends on a distance of the memory block from an edge of the array. The storage circuitry is configured to apply to the memory blocks programming cycles so that a number of programming cycles that can be applied to a respective memory block is based on a respective distance of the respective memory block from the edge of the array.

8. 发明授权

US09952779B2 Parallel scheduling of write commands to multiple memory devices 有权
公开(公告)号：US09952779B2
公开(公告)日：2018-04-24
申请号：US15057145
申请日：2016-03-01
申请人： Apple Inc.
发明人： Yoni Labenski , Roman Gindin , Etai Zaltsman , Moti Altahan , Yoram Harel , Barak Baum
IPC分类号： G06F12/00 , G06F3/06
CPC分类号： G06F3/0613 , G06F3/0647 , G06F3/0659 , G06F3/0683 , G06F3/0688
摘要： A controller includes an interface and a processor. The interface is configured to communicate with multiple memory devices over a link. The processor is configured to select at least first and second memory devices for writing, and to write at least first and second data units in sequence to the first memory device over the link, while avoiding writing to any of the other memory devices until transferal of the at least first and second data units over the link has been completed, to write at least one data unit to the second memory device after transferring the at least first and second data units to the first memory device, and, in response to verifying that the first memory device is ready to receive subsequent data, to write to the first memory device at least a third data unit.

9. 发明授权

US09330783B1 Identifying word-line-to-substrate and word-line-to-word-line short-circuit events in a memory block 有权
标题翻译：识别存储器块中的字线到基板和字线到字线的短路事件
公开(公告)号：US09330783B1
公开(公告)日：2016-05-03
申请号：US14572818
申请日：2014-12-17
申请人： APPLE INC.
发明人： Barak Rotbard , Avraham Poza Meir , Eyal Gurgi , Yael Shur , Barak Baum
IPC分类号： G11C29/00 , G11C29/02 , G11C16/26 , G11C16/14
CPC分类号： G11C29/025 , G11C29/006 , G11C2029/1202
摘要： An apparatus includes a memory and a memory controller. The memory includes a memory block that includes memory cells connected by word lines. The memory controller is configured to store data in the memory cells, and to identify a suspected short-circuit event in the memory block by recognizing a deviation of a performance characteristic of at least a given word line in the memory block relative to the performance characteristic of remaining word lines in the memory block.
摘要翻译：一种装置包括存储器和存储器控制器。该存储器包括一个包含通过字线连接的存储器单元的存储块。存储器控制器被配置为将数据存储在存储器单元中，并且通过识别存储器块中的至少给定字线的性能特性相对于性能特性的偏差来识别存储器块中的可疑短路事件剩余字线在存储器块中。

10. 发明申请

US20150200016A1 STORAGE IN CHARGE-TRAP MEMORY STRUCTURES USING ADDITIONAL ELECTRICALLY-CHARGED REGIONS 有权
标题翻译：使用附加电费区的充电轨迹存储结构中的存储
公开(公告)号：US20150200016A1
公开(公告)日：2015-07-16
申请号：US14457380
申请日：2014-08-12
申请人： Apple Inc.
发明人： Arik Rizel , Avraham Poza Meir , Yael Shur , Eyal Gurgi , Barak Baum
IPC分类号： G11C16/26 , G11C16/10
CPC分类号： G11C16/24 , G11C11/5671 , G11C16/0466 , G11C16/0475 , G11C16/10 , G11C16/26 , H01L27/11568 , H01L29/42328
摘要： A device includes a memory and a read/write (R/W) unit. The memory includes multiple gates coupled to a common charge-trap layer. The R/W unit is configured to program and read the memory by creating and reading a set of electrically-charged regions in the common charge-trap layer, wherein at least a given region in the set is not uniquely associated with any single one of the gates.
摘要翻译：一个设备包括一个存储器和一个读/写（R / W）单元。存储器包括耦合到公共电荷陷阱层的多个门。 R / W单元被配置为通过在公共电荷陷阱层中创建和读取一组充电区域来对存储器进行编程和读取，其中集合中的至少一个给定区域不是唯一地与大门。

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