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1. 发明申请

US20180088622A1 ADAPTIVE RATE-MATCHING FIRST-IN FIRST-OUT (FIFO) SYSTEM 审中-公开
公开(公告)号：US20180088622A1
公开(公告)日：2018-03-29
申请号：US15274597
申请日：2016-09-23
申请人： Altera Corporation
发明人： Han Hua Leong , Ru Yin Ng , Geok Sun Chong , David W. Mendel
IPC分类号： G06F1/08 , G06F13/40
CPC分类号： G06F1/08 , G06F13/4068
摘要： A control system controls First-In First-Out (FIFO) settings of a receiving system. The control system includes a FIFO settings controller that receives a first signal indicative of a first frequency of data received by the receiving system. The FIFO settings controller receives a second signal indicative of a second frequency of a clock that reads the data received by the receiving system. The FIFO settings controller determines a difference (e.g., a parts-per-million (PPM) difference) between the first frequency and the second frequency. The FIFO settings controller sends a third signal indicative of instructions to adjust FIFO configuration settings based on the PPM difference.

2. 发明授权

US09106504B1 Methods and apparatus for aligning signals in transceiver circuitry 有权
标题翻译：在收发器电路中对准信号的方法和装置
公开(公告)号：US09106504B1
公开(公告)日：2015-08-11
申请号：US14055063
申请日：2013-10-16
申请人： Altera Corporation
发明人： Chiang Wei Lee , Han Hua Leong , Keen Yew Loke , Siew Leong Lam
IPC分类号： H04L5/16 , H04L25/40
CPC分类号： H04L25/14
摘要： Transceiver circuitry may include a storage element that receives data signals from an external element, an alignment detector circuit, and a register. The storage element has a write clock terminal that receives a channel clock signal and a read clock terminal that receives another channel clock signal. The alignment detector circuit is adapted to generate an asserted ready signal when a predefined pattern is detected in the received data signals. The register receives an output signal from the storage element and outputs the output signal based on the asserted ready signal that is generated by the alignment detector circuit. The register may be clocked by the same channel clock signal that is received at the read clock terminal of the storage element.
摘要翻译：收发器电路可以包括从外部元件接收数据信号的存储元件，对准检测器电路和寄存器。存储元件具有接收通道时钟信号的写时钟端子和接收另一通道时钟信号的读时钟端子。当在所接收的数据信号中检测到预定模式时，对准检测器电路适于产生断言的就绪信号。该寄存器接收来自存储元件的输出信号，并且基于由对准检测器电路产生的被断言就绪信号输出输出信号。寄存器可以由在存储元件的读取时钟端接收的相同通道时钟信号来计时。

3. 发明授权

US10417169B1 Methods and apparatus for high-speed serial interface link assist 有权
公开(公告)号：US10417169B1
公开(公告)日：2019-09-17
申请号：US15264293
申请日：2016-09-13
申请人： ALTERA CORPORATION
发明人： Han Hua Leong , Suresh Gordhanlal Andani , Peter Schepers
IPC分类号： G06F11/00 , G06F13/00 , G06F13/42 , G06F13/10 , G06F13/20 , G06F11/07
摘要： The present disclosure provides a link assist capability that may be added to a compiled design that includes a transceiver. The transceiver with the link assist capability may be dynamically reconfigured to operate in a link assist mode, which is a diagnostic and test mode. The link assist mode may interact with a HSSI link partner, or a design software tool, or a user-defined program. The link assist mode may also facilitate remote debugging. One embodiment relates to an apparatus for serial interface link assist. Another embodiment relates to a method of dynamic reconfiguration of transceiver settings. Another embodiment relates to a method of tuning a bidirectional serial link. Other features, aspects and embodiments are also disclosed.

4. 发明授权

US09268888B1 Latency computation circuitry 有权
标题翻译：延迟计算电路
公开(公告)号：US09268888B1
公开(公告)日：2016-02-23
申请号：US13889033
申请日：2013-05-07
申请人： Altera Corporation
发明人： Han Hua Leong , Si Xing Saw , Seng Kuan Yeow
IPC分类号： H04J3/06 , G06F17/50
CPC分类号： G06F13/00 , G06F13/4291
摘要： An integrated circuit may include multiple circuit blocks, each with an associated latency value. As an example, transceiver circuitry in an integrated circuit may receive different data packets and circuit blocks in the transceiver circuitry may have different latency values depending on the data packets received. The integrated circuit may further include latency computation circuitry that receives the different latency values from the multiple circuit blocks. The latency computation circuitry may accordingly output a total latency value for the multiple circuit blocks in the integrated circuit based on the received latency values.
摘要翻译：集成电路可以包括多个电路块，每个具有相关的等待时间值。作为示例，集成电路中的收发器电路可以接收不同的数据分组，并且收发器电路中的电路块可以具有取决于所接收的数据分组的不同等待时间值。集成电路还可以包括从多个电路块接收不同等待时间值的等待时间计算电路。因此等待时间计算电路可以基于接收到的等待时间值输出集成电路中的多个电路块的总等待时间值。

5. 发明授权

US10146249B2 Adaptive rate-matching first-in first-out (FIFO) system 有权
公开(公告)号：US10146249B2
公开(公告)日：2018-12-04
申请号：US15274597
申请日：2016-09-23
申请人： Altera Corporation
发明人： Han Hua Leong , Ru Yin Ng , Geok Sun Chong , David W. Mendel
IPC分类号： H04L7/00 , G06F1/08 , G06F13/40
摘要： A control system controls First-In First-Out (FIFO) settings of a receiving system. The control system includes a FIFO settings controller that receives a first signal indicative of a first frequency of data received by the receiving system. The FIFO settings controller receives a second signal indicative of a second frequency of a clock that reads the data received by the receiving system. The FIFO settings controller determines a difference (e.g., a parts-per-million (PPM) difference) between the first frequency and the second frequency. The FIFO settings controller sends a third signal indicative of instructions to adjust FIFO configuration settings based on the PPM difference.

6. 发明授权

US09774478B1 Low-skew channel bonding using phase-measuring FIFO buffer 有权
公开(公告)号：US09774478B1
公开(公告)日：2017-09-26
申请号：US14676583
申请日：2015-04-01
申请人： ALTERA CORPORATION
发明人： David W. Mendel , Han Hua Leong
IPC分类号： H04L25/14 , H04L12/24 , H04L12/875 , H04L12/26
CPC分类号： H04L25/14 , G06F5/06 , H04L41/0896 , H04L43/087 , H04L47/56
摘要： Circuits and methods are disclosed for low-skew bonding of a plurality of data channels into a multi-lane data channel. In one embodiment, phase-measuring first-in first-out buffer circuits buffer pre-buffer parallel data signals and generate phase-measurement signals. A channel-bonding control circuit receives the phase-measurement signals and generates bit-slip control signals. Transmission bit-slip circuits slip integer numbers of bits based on the bit-slip control signals. Bypass registers may be used when the integer number of bits is greater or equal to the parallel width of a lane. In another embodiment, the channel-bonding control circuit receives the phase-measurement signals from the phase-measuring FIFO buffer circuits and generates clock-slip control signals. Clock slip circuits controllably slip parallel clock signals by integer numbers of unit intervals of a serial clock signal. Various other aspects, features, and embodiments are also disclosed.

7. 发明授权

US09246497B1 Integrated circuit (IC) clocking techniques 有权
标题翻译：集成电路（IC）时钟技术
公开(公告)号：US09246497B1
公开(公告)日：2016-01-26
申请号：US14286767
申请日：2014-05-23
申请人： Altera Corporation
发明人： Han Hua Leong
IPC分类号： H03D3/24 , H03L7/08 , H03L7/10
CPC分类号： H03L7/0807 , H03L7/07 , H03L7/0812 , H03L7/087 , H03L7/10 , H04L7/033 , H04L7/10
摘要： Circuits and techniques for operating an integrated circuit (IC) are disclosed. A disclosed circuit includes a divider circuit that is operable to receive a first signal at a first speed and output a second signal at a second speed based on the first signal. A recovery circuit is coupled to the divider circuit. The recovery circuit is operable to determine the frequency of the second signal and is further operable to generate a first ready signal and a recovered clock signal based on the second signal. A phase aligner circuit, operable to align a phase of the second signal with a phase of the recovered clocks signal based on the first ready signal, is coupled to the recovery circuit.
摘要翻译：公开了用于操作集成电路（IC）的电路和技术。所公开的电路包括分频器电路，其可操作以基于第一信号以第一速度接收第一信号并以第二速度输出第二信号。恢复电路耦合到分频器电路。恢复电路可操作以确定第二信号的频率，并且还可操作以基于第二信号产生第一就绪信号和恢复的时钟信号。相位对准器电路，可操作以将第二信号的相位与基于第一就绪信号的恢复的时钟信号的相位对准，并将其耦合到恢复电路。

8. 发明授权

US10291442B2 Low-skew channel bonding using phase-measuring FIFO buffer 有权
公开(公告)号：US10291442B2
公开(公告)日：2019-05-14
申请号：US15684310
申请日：2017-08-23
申请人： ALTERA CORPORATION
发明人： David W. Mendel , Han Hua Leong
IPC分类号： H04L25/14 , H04L12/24 , H04L12/26 , H04L12/875 , G06F5/06
摘要： Circuits and methods are disclosed for low-skew bonding of a plurality of data channels into a multi-lane data channel. In one embodiment, phase-measuring first-in first-out buffer circuits buffer pre-buffer parallel data signals and generate phase-measurement signals. A channel-bonding control circuit receives the phase-measurement signals and generates bit-slip control signals. Transmission bit-slip circuits slip integer numbers of bits based on the bit-slip control signals. Bypass registers may be used when the integer number of bits is greater or equal to the parallel width of a lane. In another embodiment, the channel-bonding control circuit receives the phase-measurement signals from the phase-measuring FIFO buffer circuits and generates clock-slip control signals. Clock slip circuits controllably slip parallel clock signals by integer numbers of unit intervals of a serial clock signal. Various other aspects, features, and embodiments are also disclosed.

9. 发明授权

US09465769B1 Methods and apparatus for high-speed serial interface link assist 有权
标题翻译：高速串行接口链路辅助的方法和装置
公开(公告)号：US09465769B1
公开(公告)日：2016-10-11
申请号：US14982664
申请日：2015-12-29
申请人： ALTERA CORPORATION
发明人： Han Hua Leong , Suresh Gordhanlal Andani , Peter Schepers
IPC分类号： G06F11/267 , G06F13/42 , G06F13/40 , G06F11/07 , G06F11/263
CPC分类号： G06F13/4286 , G06F11/221 , G06F11/263 , G06F11/267 , G06F13/4022
摘要： The present disclosure provides a link assist capability that may be added to a compiled design that includes a transceiver. The transceiver with the link assist capability may be dynamically reconfigured to operate in a link assist mode, which is a diagnostic and test mode. The link assist mode may interact with a HSSI link partner, or a design software tool, or a user-defined program. The link assist mode may also facilitate remote debugging. One embodiment relates to an apparatus for serial interface link assist. Another embodiment relates to a method of dynamic reconfiguration of transceiver settings. Another embodiment relates to a method of tuning a bidirectional serial link. Other features, aspects and embodiments are also disclosed.
摘要翻译：本公开提供了可以被添加到包括收发器的编译设计的链接辅助能力。具有链路辅助功能的收发器可以被动态地重新配置为在作为诊断和测试模式的链路辅助模式中操作。链路辅助模式可以与HSSI链路伙伴或设计软件工具或用户定义的程序交互。链接辅助模式也可以方便远程调试。一个实施例涉及用于串行接口链路辅助的装置。另一实施例涉及收发机设置的动态重新配置的方法。另一实施例涉及一种调整双向串行链路的方法。还公开了其它特征，方面和实施例。

10. 发明授权

US09100112B1 Latency built-in self-test 有权
标题翻译：延迟内置自检
公开(公告)号：US09100112B1
公开(公告)日：2015-08-04
申请号：US14331973
申请日：2014-07-15
申请人： Altera Corporation
发明人： Han Hua Leong , Yanjing Ke
IPC分类号： H04B3/46 , H04B17/00
CPC分类号： G06F11/27
摘要： Techniques and mechanisms determine latencies of transmitters of transceivers and use the determined latencies to adjust latencies of the transmitters. For example, a test pattern may be used to determine a first transmitter has a higher latency than a second transmitter. The second transmitter may be provided data indicating a delay to increase its latency such that it matches the first transmitter.
摘要翻译：技术和机制确定收发器发射机的延迟，并使用确定的延迟来调整发射机的延迟。例如，可以使用测试模式来确定第一发射机具有比第二发射机更高的等待时间。可以提供第二发射机，其指示延迟以增加其等待时间，使得其与第一发射机匹配。

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