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1. 发明申请

US20160049181A1 VIRTUAL MEMORY MAPPING FOR IMPROVED DRAM PAGE LOCALITY 有权
标题翻译：用于改进DRAM页面本地化的虚拟内存映射
公开(公告)号：US20160049181A1
公开(公告)日：2016-02-18
申请号：US14460550
申请日：2014-08-15
申请人： Advanced Micro Devices, Inc.
发明人： Syed Ali Jafri , Yasuko Eckert , Srilatha Manne , Mithuna S. Thottethodi
IPC分类号： G11C7/10 , G06F12/10 , G11C11/406
CPC分类号： G06F12/1009 , G06F2212/1024 , G06F2212/654 , G06F2212/655 , G06F2212/656
摘要： Embodiments are described for methods and systems for mapping virtual memory pages to physical memory pages by analyzing a sequence of memory-bound accesses to the virtual memory pages, determining a degree of contiguity between the accessed virtual memory pages, and mapping sets of the accessed virtual memory pages to respective single physical memory pages. Embodiments are also described for a method for increasing locality of memory accesses to DRAM in virtual memory systems by analyzing a pattern of virtual memory accesses to identify contiguity of accessed virtual memory pages, predicting contiguity of the accessed virtual memory pages based on the pattern, and mapping the identified and predicted contiguous virtual memory pages to respective single physical memory pages.
摘要翻译：描述了通过分析对虚拟存储器页面的存储器绑定访问的序列，确定所访问的虚拟存储器页面之间的连续程度以及访问的虚拟存储器页面的映射集合来将虚拟存储器页面映射到物理存储器页面的方法和系统的实施例存储页面到相应的单个物理存储器页面。还描述了用于通过分析虚拟存储器访问的模式以识别所访问的虚拟存储器页的邻接性，基于该模式来预测所访问的虚拟存储器页的邻接性的方法来增加虚拟存储器系统中对DRAM的存储器访问的局部性的方法，以及将所识别的和预测的连续虚拟存储器页面映射到相应的单个物理存储器页面。

2. 发明申请

US20150357306A1 DIE-STACKED DEVICE WITH PARTITIONED MULTI-HOP NETWORK 有权
标题翻译：具有分层多路网络的DIE堆叠设备
公开(公告)号：US20150357306A1
公开(公告)日：2015-12-10
申请号：US14715023
申请日：2015-05-18
申请人： Advanced Micro Devices, Inc.
发明人： Mithuna S. Thottethodi , Gabriel H. Loh
IPC分类号： H01L25/065 , H01L23/498 , H04L12/755 , H01L23/48
CPC分类号： H04L45/021 , G06F17/5068 , H01L23/481 , H01L23/49838 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L23/5389 , H01L25/0652 , H01L25/18 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06544 , H01L2924/1461 , H01L2924/15192 , H04L45/00 , H01L2924/00
摘要： An electronic assembly includes horizontally-stacked die disposed at an interposer, and may also include vertically-stacked die. The stacked die are interconnected via a multi-hop communication network that is partitioned into a link partition and a router partition. The link partition is at least partially implemented in the metal layers of the interposer for horizontally-stacked die. The link partition may also be implemented in part by the intra-die interconnects in a single die and by the inter-die interconnects connecting vertically-stacked sets of die. The router partition is implemented at some or all of the die disposed at the interposer and comprises the logic that supports the functions that route packets among the components of the processing system via the interconnects of the link partition. The router partition may implement fixed routing, or alternatively may be configurable using programmable routing tables or configurable logic blocks.
摘要翻译：电子组件包括设置在插入器处的水平堆叠的管芯，并且还可以包括垂直堆叠的管芯。堆叠的管芯通过被划分成链路分区和路由器分区的多跳通信网络相互连接。连接分隔件至少部分地实现在用于水平堆叠的模具的插入件的金属层中。链路分区还可以部分地由单个管芯中的管芯内互连和通过垂直堆叠的管芯组连接的晶片间互连来实现。路由器分区在设置在插入器处的部分或全部芯片上实现，并且包括支持经由链路分区的互连来在处理系统的组件之间路由分组的功能的逻辑。路由器分区可以实现固定路由，或者可以使用可编程路由表或可配置逻辑块来配置。

3. 发明申请

US20140181412A1 MECHANISMS TO BOUND THE PRESENCE OF CACHE BLOCKS WITH SPECIFIC PROPERTIES IN CACHES 有权
标题翻译：在缓存中具有特定属性的高速缓存块的存在机制
公开(公告)号：US20140181412A1
公开(公告)日：2014-06-26
申请号：US13725011
申请日：2012-12-21
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Mithuna S. Thottethodi , Gabriel H. Loh , James M. O'Connor , Yasuko Eckert , Bradford M. Beckmann
IPC分类号： G06F12/08
CPC分类号： G06F12/0871 , G06F12/0848
摘要： A system and method for efficiently limiting storage space for data with particular properties in a cache memory. A computing system includes a cache and one or more sources for memory requests. In response to receiving a request to allocate data of a first type, a cache controller allocates the data in the cache responsive to determining a limit of an amount of data of the first type permitted in the cache is not reached. The controller maintains an amount and location information of the data of the first type stored in the cache. Additionally, the cache may be partitioned with each partition designated for storing data of a given type. Allocation of data of the first type is dependent at least upon the availability of a first partition and a limit of an amount of data of the first type in a second partition.
摘要翻译：一种用于有效地限制高速缓冲存储器中具有特定属性的数据的存储空间的系统和方法。计算系统包括缓存和用于存储器请求的一个或多个源。响应于接收到分配第一类型的数据的请求，高速缓存控制器响应于确定未达到高速缓存中允许的第一类型的数据量的极限而分配缓存中的数据。控制器维护存储在高速缓存中的第一类型的数据的量和位置信息。此外，可以用指定用于存储给定类型的数据的每个分区对高速缓存进行分区。第一类型的数据的分配至少依赖于第一分区的可用性和第二分区中第一类型的数据量的限制。

4. 发明授权

US09075730B2 Mechanisms to bound the presence of cache blocks with specific properties in caches 有权
标题翻译：限制缓存中具有特定属性的高速缓存块的存在的机制
公开(公告)号：US09075730B2
公开(公告)日：2015-07-07
申请号：US13725011
申请日：2012-12-21
申请人： Advanced Micro Devices, Inc.
发明人： Mithuna S. Thottethodi , Gabriel H. Loh , James M. O'Connor , Yasuko Eckert , Bradford M. Beckmann
IPC分类号： G06F12/08
CPC分类号： G06F12/0871 , G06F12/0848
摘要： A system and method for efficiently limiting storage space for data with particular properties in a cache memory. A computing system includes a cache and one or more sources for memory requests. In response to receiving a request to allocate data of a first type, a cache controller allocates the data in the cache responsive to determining a limit of an amount of data of the first type permitted in the cache is not reached. The controller maintains an amount and location information of the data of the first type stored in the cache. Additionally, the cache may be partitioned with each partition designated for storing data of a given type. Allocation of data of the first type is dependent at least upon the availability of a first partition and a limit of an amount of data of the first type in a second partition.
摘要翻译：一种用于有效地限制高速缓冲存储器中具有特定属性的数据的存储空间的系统和方法。计算系统包括缓存和用于存储器请求的一个或多个源。响应于接收到分配第一类型的数据的请求，高速缓存控制器响应于确定未达到高速缓存中允许的第一类型的数据量的极限而分配缓存中的数据。控制器维护存储在高速缓存中的第一类型的数据的量和位置信息。此外，可以用指定用于存储给定类型的数据的每个分区对高速缓存进行分区。第一类型的数据的分配至少依赖于第一分区的可用性和第二分区中第一类型的数据量的限制。

5. 发明申请

US20140177626A1 DIE-STACKED DEVICE WITH PARTITIONED MULTI-HOP NETWORK 有权
标题翻译：具有分层多路网络的DIE堆叠设备
公开(公告)号：US20140177626A1
公开(公告)日：2014-06-26
申请号：US13726142
申请日：2012-12-23
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Mithuna S. Thottethodi , Gabriel H. Loh
IPC分类号： H04L12/56 , H01L23/498
CPC分类号： H04L45/021 , G06F17/5068 , H01L23/481 , H01L23/49838 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L23/5389 , H01L25/0652 , H01L25/18 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06544 , H01L2924/1461 , H01L2924/15192 , H04L45/00 , H01L2924/00
摘要： An electronic assembly includes horizontally-stacked die disposed at an interposer, and may also include vertically-stacked die. The stacked die are interconnected via a multi-hop communication network that is partitioned into a link partition and a router partition. The link partition is at least partially implemented in the metal layers of the interposer for horizontally-stacked die. The link partition may also be implemented in part by the intra-die interconnects in a single die and by the inter-die interconnects connecting vertically-stacked sets of die. The router partition is implemented at some or all of the die disposed at the interposer and comprises the logic that supports the functions that route packets among the components of the processing system via the interconnects of the link partition. The router partition may implement fixed routing, or alternatively may be configurable using programmable routing tables or configurable logic blocks.
摘要翻译：电子组件包括设置在插入器处的水平堆叠的管芯，并且还可以包括垂直堆叠的管芯。堆叠的管芯通过被划分成链路分区和路由器分区的多跳通信网络相互连接。连接分隔件至少部分地实现在用于水平堆叠的模具的插入件的金属层中。链路分区还可以部分地由单个管芯中的管芯内互连和通过垂直堆叠的管芯组连接的晶片间互连来实现。路由器分区在设置在插入器处的部分或全部芯片上实现，并且包括支持通过链路分区的互连来在处理系统的组件之间路由分组的功能的逻辑。路由器分区可以实现固定路由，或者可以使用可编程路由表或可配置逻辑块来配置。

6. 发明申请

US20140143505A1 Dynamically Configuring Regions of a Main Memory in a Write-Back Mode or a Write-Through Mode 有权
标题翻译：以写回模式或直写模式动态配置主内存区域
公开(公告)号：US20140143505A1
公开(公告)日：2014-05-22
申请号：US13736063
申请日：2013-01-07
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Jaewoong Sim , Mithuna S. Thottethodi , Gabriel H. Loh
IPC分类号： G06F12/08
CPC分类号： G06F12/0802 , G06F12/0804 , G06F12/0862 , G06F12/0888
摘要： The described embodiments include a main memory and a cache memory (or “cache”) with a cache controller that includes a mode-setting mechanism. In some embodiments, the mode-setting mechanism is configured to dynamically determine an access pattern for the main memory. Based on the determined access pattern, the mode-setting mechanism configures at least one region of the main memory in a write-back mode and configures other regions of the main memory in a write-through mode. In these embodiments, when performing a write operation in the cache memory, the cache controller determines whether a region in the main memory where the cache block is from is configured in the write-back mode or the write-through mode and then performs a corresponding write operation in the cache memory
摘要翻译：所描述的实施例包括具有包括模式设置机制的高速缓存控制器的主存储器和高速缓冲存储器（或“高速缓存”）。在一些实施例中，模式设置机制被配置为动态地确定主存储器的访问模式。基于确定的访问模式，模式设置机制以回写模式配置主存储器的至少一个区域，并以直通模式配置主存储器的其他区域。在这些实施例中，当在高速缓冲存储器中执行写入操作时，高速缓存控制器确定高速缓存块所处的主存储器中的区域是否配置在回写模式或直写模式中，然后执行相应的在高速缓存中写入操作

7. 发明授权

US09766936B2 Selecting a resource from a set of resources for performing an operation 有权
公开(公告)号：US09766936B2
公开(公告)日：2017-09-19
申请号：US14935056
申请日：2015-11-06
申请人： Advanced Micro Devices, Inc.
发明人： Bradford M. Beckmann , Mithuna S. Thottethodi , James M. O'Connor , Mauricio Breternitz , Lisa R. Hsu , Gabriel H. Loh , Yasuko Eckert
IPC分类号： G06F9/50 , G06F12/0875
CPC分类号： G06F9/5016 , G06F9/5011 , G06F12/0875 , G06F2212/45
摘要： The described embodiments comprise a selection mechanism that selects a resource from a set of resources in a computing device for performing an operation. In some embodiments, the selection mechanism performs a lookup in a table selected from a set of tables to identify a resource from the set of resources. When the resource is not available for performing the operation and until another resource is selected for performing the operation, the selection mechanism identifies a next resource in the table and selects the next resource for performing the operation when the next resource is available for performing the operation.

8. 发明授权

US09552294B2 Dynamically configuring regions of a main memory in a write-back mode or a write-through mode 有权
标题翻译：以写回模式或直写模式动态配置主存储器的区域
公开(公告)号：US09552294B2
公开(公告)日：2017-01-24
申请号：US13736063
申请日：2013-01-07
申请人： Advanced Micro Devices, Inc.
发明人： Jaewoong Sim , Mithuna S. Thottethodi , Gabriel H. Loh
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0802 , G06F12/0804 , G06F12/0862 , G06F12/0888
摘要： The described embodiments include a main memory and a cache memory (or “cache”) with a cache controller that includes a mode-setting mechanism. In some embodiments, the mode-setting mechanism is configured to dynamically determine an access pattern for the main memory. Based on the determined access pattern, the mode-setting mechanism configures at least one region of the main memory in a write-back mode and configures other regions of the main memory in a write-through mode. In these embodiments, when performing a write operation in the cache memory, the cache controller determines whether a region in the main memory where the cache block is from is configured in the write-back mode or the write-through mode and then performs a corresponding write operation in the cache memory.
摘要翻译：所描述的实施例包括具有包括模式设置机制的高速缓存控制器的主存储器和高速缓冲存储器（或“高速缓存”）。在一些实施例中，模式设置机制被配置为动态地确定主存储器的访问模式。基于确定的访问模式，模式设置机制以回写模式配置主存储器的至少一个区域，并以直通模式配置主存储器的其他区域。在这些实施例中，当在高速缓冲存储器中执行写入操作时，高速缓存控制器确定高速缓存块所处的主存储器中的区域是否配置在回写模式或直写模式中，然后执行相应的在高速缓存中写入操作。

9. 发明授权

US09251069B2 Mechanisms to bound the presence of cache blocks with specific properties in caches 有权
标题翻译：限制缓存中具有特定属性的高速缓存块的存在的机制
公开(公告)号：US09251069B2
公开(公告)日：2016-02-02
申请号：US14055869
申请日：2013-10-16
申请人： Advanced Micro Devices, Inc.
发明人： Yasuko Eckert , Gabriel H. Loh , Mauricio Breternitz , James M. O'Connor , Srilatha Manne , Nuwan S. Jayasena , Mithuna S. Thottethodi
IPC分类号： G06F12/08
CPC分类号： G06F12/0808 , G06F1/3225 , G06F1/3275 , G06F12/0848 , G06F12/0888 , G06F12/0897 , Y02D10/13 , Y02D10/14
摘要： A system and method for efficiently limiting storage space for data with particular properties in a cache memory. A computing system includes a cache array and a corresponding cache controller. The cache array includes multiple banks, wherein a first bank is powered down. In response a write request to a second bank for data indicated to be stored in the powered down first bank, the cache controller determines a respective bypass condition for the data. If the bypass condition exceeds a threshold, then the cache controller invalidates any copy of the data stored in the second bank. If the bypass condition does not exceed the threshold, then the cache controller stores the data with a clean state in the second bank. The cache controller writes the data in a lower-level memory for both cases.
摘要翻译：一种用于有效地限制高速缓冲存储器中具有特定属性的数据的存储空间的系统和方法。计算系统包括高速缓存阵列和对应的高速缓存控制器。高速缓存阵列包括多个存储体，其中第一存储体断电。作为响应，向第二存储体写入请求以指示存储在掉电第一存储体中的数据，高速缓存控制器确定数据的相应旁路条件。如果旁路条件超过阈值，则高速缓存控制器使存储在第二组中的数据的任何副本无效。如果旁路条件不超过阈值，则高速缓存控制器将具有干净状态的数据存储在第二存储体中。高速缓存控制器将这些数据写入较低级别的内存。

10. 发明授权

US09065722B2 Die-stacked device with partitioned multi-hop network 有权
标题翻译：具有划分的多跳网络的堆叠式堆叠设备
公开(公告)号：US09065722B2
公开(公告)日：2015-06-23
申请号：US13726142
申请日：2012-12-23
申请人： Advanced Micro Devices, Inc.
发明人： Mithuna S. Thottethodi , Gabriel H. Loh
IPC分类号： G06F17/50 , H04L12/755 , H01L23/48 , H01L23/538 , H01L25/065 , H04L12/701 , H01L25/18
CPC分类号： H04L45/021 , G06F17/5068 , H01L23/481 , H01L23/49838 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L23/5389 , H01L25/0652 , H01L25/18 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06544 , H01L2924/1461 , H01L2924/15192 , H04L45/00 , H01L2924/00
摘要： An electronic assembly includes horizontally-stacked die disposed at an interposer, and may also include vertically-stacked die. The stacked die are interconnected via a multi-hop communication network that is partitioned into a link partition and a router partition. The link partition is at least partially implemented in the metal layers of the interposer for horizontally-stacked die. The link partition may also be implemented in part by the intra-die interconnects in a single die and by the inter-die interconnects connecting vertically-stacked sets of die. The router partition is implemented at some or all of the die disposed at the interposer and comprises the logic that supports the functions that route packets among the components of the processing system via the interconnects of the link partition. The router partition may implement fixed routing, or alternatively may be configurable using programmable routing tables or configurable logic blocks.
摘要翻译：电子组件包括设置在插入器处的水平堆叠的管芯，并且还可以包括垂直堆叠的管芯。堆叠的管芯通过被划分成链路分区和路由器分区的多跳通信网络相互连接。连接分隔件至少部分地实现在用于水平堆叠的模具的插入件的金属层中。链路分区还可以部分地由单个管芯中的管芯内互连和通过垂直堆叠的管芯组连接的晶片间互连来实现。路由器分区在设置在插入器处的部分或全部芯片上实现，并且包括支持通过链路分区的互连来在处理系统的组件之间路由分组的功能的逻辑。路由器分区可以实现固定路由，或者可以使用可编程路由表或可配置逻辑块来配置。

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