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1. 发明授权

US5991843A Method and system for concurrent computer transaction processing 有权
公开(公告)号：US5991843A
公开(公告)日：1999-11-23
申请号：US176059
申请日：1998-10-20
申请人： A. Kent Porterfield , Paul A. LaBerge , Joe M. Jeddeloh
发明人： A. Kent Porterfield , Paul A. LaBerge , Joe M. Jeddeloh
IPC分类号： G06F13/36 , G06F13/40
CPC分类号： G06F13/4027 , G06F13/36 , G06F13/405
摘要： A computer system and method concurrently process transactions directed to computer devices coupled to a bus agent. The method transmits first and second transaction requests from one or more computer processors across a computer bus to the bus agent. The bus agent transmits the first transaction request to a first computer device coupled to the bus agent. In addition, the bus agent transmits the second transaction request to a second computer device before the bus agent has received a transaction response to the first transaction request from the first computer device, thereby concurrently processing the transaction requests. The bus agent includes plural device managers each uniquely associated with one of the computer devices. Each device manager employs a queue pointer into a transaction queue to track each transaction involving the computer device associated with the device. manager.

2. 发明授权

US5878235A Method and system for concurrent computer transaction processing 失效
标题翻译：并发计算机事务处理的方法和系统
公开(公告)号：US5878235A
公开(公告)日：1999-03-02
申请号：US725576
申请日：1996-10-03
申请人： A. Kent Porterfield , Paul A. Laberge , Joe M. Jeddeloh
发明人： A. Kent Porterfield , Paul A. Laberge , Joe M. Jeddeloh
IPC分类号： G06F13/36 , G06F13/40
CPC分类号： G06F13/4027 , G06F13/36 , G06F13/405
摘要： A computer system and method concurrently process transactions directed to computer devices coupled to a bus agent. The method transmits first and second transaction requests from one or more computer processors across a computer bus to the bus agent. The bus agent transmits the first transaction request to a first computer device coupled to the bus agent. In addition, the bus agent transmits the second transaction request to a second computer device before the bus agent has received a transaction response to the first transaction request from the first computer device, thereby concurrently processing the transaction requests. The bus agent includes plural device managers each uniquely associated with one of the computer devices. Each device manager employs a queue pointer into a transaction queue to track each transaction involving the computer device associated with the device manager.
摘要翻译：计算机系统和方法同时处理指向耦合到总线代理的计算机设备的事务。该方法通过计算机总线将一个或多个计算机处理器的第一和第二事务请求发送到总线代理。总线代理将第一事务请求发送到耦合到总线代理的第一计算机设备。此外，总线代理在总线代理已经从第一计算机设备接收到对第一事务请求的事务响应之前，将第二事务请求发送到第二计算机设备，从而同时处理事务请求。总线代理包括多个设备管理器，每个设备管理器与计算机设备之一唯一地相关联。每个设备管理器使用队列指针到事务队列中以跟踪涉及与设备管理器相关联的计算机设备的每个事务。

3. 发明授权

US5978872A Method and system for concurrent computer transaction processing 失效
标题翻译：并发计算机事务处理的方法和系统
公开(公告)号：US5978872A
公开(公告)日：1999-11-02
申请号：US66526
申请日：1998-04-24
申请人： A. Kent Porterfield , Paul A. LaBerge , Joe M. Jeddeloh
发明人： A. Kent Porterfield , Paul A. LaBerge , Joe M. Jeddeloh
IPC分类号： G06F13/36 , G06F13/40
CPC分类号： G06F13/4027 , G06F13/36 , G06F13/405
摘要： A computer system and method concurrently process transactions directed to computer devices coupled to a bus agent. The method transmits first and second transaction requests from one or more computer processors across a computer bus to the bus agent. The bus agent transmits the first transaction request to a first computer device coupled to the bus agent. In addition, the bus agent transmits the second transaction request to a second computer device before the bus agent has received a transaction response to the first transaction request from the first computer device, thereby concurrently processing the transaction requests. The bus agent includes plural device managers each uniquely associated with one of the computer devices. Each device manager employs a queue pointer into a transaction queue to track each transaction involving the computer device associated with the device. manager.
摘要翻译：计算机系统和方法同时处理指向耦合到总线代理的计算机设备的事务。该方法通过计算机总线将一个或多个计算机处理器的第一和第二事务请求发送到总线代理。总线代理将第一事务请求发送到耦合到总线代理的第一计算机设备。此外，总线代理在总线代理已经从第一计算机设备接收到对第一事务请求的事务响应之前，将第二事务请求发送到第二计算机设备，从而同时处理事务请求。总线代理包括多个设备管理器，每个设备管理器与计算机设备之一唯一地相关联。每个设备管理器使用队列指针到事务队列中以跟踪涉及与设备相关联的计算机设备的每个事务。经理。

4. 发明授权

US08806131B2 Multi-serial interface stacked-die memory architecture 有权
标题翻译：多串行接口堆叠存储器架构
公开(公告)号：US08806131B2
公开(公告)日：2014-08-12
申请号：US13179156
申请日：2011-07-08
申请人： Joe M. Jeddeloh , Paul A. LaBerge
发明人： Joe M. Jeddeloh , Paul A. LaBerge
IPC分类号： H04L12/28 , H04L12/56 , G06F13/00 , G06F13/28
CPC分类号： G06F13/1668 , G06F13/1684 , G06F13/4022 , G06F2213/16 , Y02D10/14 , Y02D10/151
摘要： Systems and methods disclosed herein substantially concurrently transfer a plurality of streams of commands, addresses, and/or data across a corresponding plurality of serialized communication link interfaces (SCLIs) between one or more originating devices or destination devices such as a processor and a switch. At the switch, one or more commands, addresses, or data corresponding to each stream can be transferred to a corresponding destination memory vault controller (MVC) associated with a corresponding memory vault. The destination MVC can perform write operations, read operations, and/or memory vault housekeeping operations independently from concurrent operations associated with other MVCs coupled to a corresponding plurality of memory vaults.
摘要翻译：本文公开的系统和方法基本上同时传送跨越一个或多个发起设备或诸如处理器和交换机的目的地设备之间的对应多个串行化通信链路接口（SCLI）的多个命令，地址和/或数据流。在交换机上，可以将与每个流相对应的一个或多个命令，地址或数据传送到与对应的存储器保险库相关联的对应的目的地存储器保管库控制器（MVC）。目的地MVC可以独立于与耦合到对应的多个存储器库的其他MVC相关联的并行操作执行写入操作，读取操作和/或存储器保管库内务处理操作。

5. 发明授权

US08619481B2 Switched interface stacked-die memory architecture 有权
标题翻译：交换式接口堆叠式存储器架构
公开(公告)号：US08619481B2
公开(公告)日：2013-12-31
申请号：US13595294
申请日：2012-08-27
申请人： Joe M. Jeddeloh , Paul A. LaBerge
发明人： Joe M. Jeddeloh , Paul A. LaBerge
IPC分类号： G11C29/00
CPC分类号： G11C29/76 , G06F13/1668 , G06F13/4239 , G11C5/02 , G11C7/10 , G11C8/10 , G11C29/04 , Y02B70/123 , Y02B70/126 , Y02D10/14 , Y02D10/151
摘要： Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request directly to an address decoder associated with a stacked-die memory vault without knowing whether a repair address is required. If a subsequent analysis of the memory request shows that a repair address is required, an in-process decode of the requested memory address can be halted and decoding of the repair address initiated.
摘要翻译：本文公开的系统和方法包括可以接收包括所请求的存储器地址的存储器请求的那些，并且可以将存储器请求直接发送到与堆叠的存储器存储库相关联的地址解码器，而不知道是否需要修复地址。如果对存储器请求的后续分析显示需要修复地址，则可以暂停所请求的存储器地址的进程内解码并启动修复地址的解码。

6. 发明申请

US20130003473A1 STACKED DEVICE REMAPPING AND REPAIR 有权
标题翻译：堆叠设备重新修复和维修
公开(公告)号：US20130003473A1
公开(公告)日：2013-01-03
申请号：US13616704
申请日：2012-09-14
申请人： Brent Keeth , Chris G. Martin , Troy A. Manning , Joe M. Jeddeloh , Timothy B. Cowles , Jim Rehmeyer , Paul A. LaBerge
发明人： Brent Keeth , Chris G. Martin , Troy A. Manning , Joe M. Jeddeloh , Timothy B. Cowles , Jim Rehmeyer , Paul A. LaBerge
IPC分类号： G11C7/10
CPC分类号： G06F12/08 , G06F12/10 , G11C5/025 , G11C29/04 , G11C29/18 , G11C29/76 , G11C29/78 , G11C29/808 , G11C29/812 , G11C29/883 , H01L2224/0554 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.
摘要翻译：各种实施例包括具有布置在堆叠中的多个骰子的装置，系统和方法，其中有缺陷的单元可以被同一裸片上的备用单元或不同的管芯替代。描述其他实施例。

7. 发明授权

US07978721B2 Multi-serial interface stacked-die memory architecture 有权
标题翻译：多串行接口堆叠存储器架构
公开(公告)号：US07978721B2
公开(公告)日：2011-07-12
申请号：US12261942
申请日：2008-10-30
申请人： Joe M. Jeddeloh , Paul A. LaBerge
发明人： Joe M. Jeddeloh , Paul A. LaBerge
IPC分类号： H04L12/28 , H04J3/00 , G06F13/00 , G06F13/28 , G11C11/00
CPC分类号： G06F13/1668 , G06F13/1684 , G06F13/4022 , G06F2213/16 , Y02D10/14 , Y02D10/151
摘要： Systems and methods disclosed herein substantially concurrently transfer a plurality of streams of commands, addresses, and/or data across a corresponding plurality of serialized communication link interfaces (SCLIs) between one or more originating devices or destination devices such as a processor and a switch. At the switch, one or more commands, addresses, or data corresponding to each stream can be transferred to a corresponding destination memory vault controller (MVC) associated with a corresponding memory vault. The destination MVC can perform write operations, read operations, and/or memory vault housekeeping operations independently from concurrent operations associated with other MVCs coupled to a corresponding plurality of memory vaults.
摘要翻译：本文公开的系统和方法基本上同时传送跨越一个或多个发起设备或诸如处理器和交换机的目的地设备之间的对应多个串行化通信链路接口（SCLI）的多个命令，地址和/或数据流。在交换机上，可以将与每个流相对应的一个或多个命令，地址或数据传送到与对应的存储器保险库相关联的对应的目的地存储器保管库控制器（MVC）。目的地MVC可以独立于与耦合到对应的多个存储器库的其他MVC相关联的并行操作执行写入操作，读取操作和/或存储器保管库内务处理操作。

8. 发明申请

US20100005238A1 MULTI-SERIAL INTERFACE STACKED-DIE MEMORY ARCHITECTURE 有权
标题翻译：多串行接口堆叠存储器架构
公开(公告)号：US20100005238A1
公开(公告)日：2010-01-07
申请号：US12261942
申请日：2008-10-30
申请人： Joe M. Jeddeloh , Paul A. LaBerge
发明人： Joe M. Jeddeloh , Paul A. LaBerge
IPC分类号： G06F13/00
CPC分类号： G06F13/1668 , G06F13/1684 , G06F13/4022 , G06F2213/16 , Y02D10/14 , Y02D10/151
摘要： Systems and methods disclosed herein substantially concurrently transfer a plurality of streams of commands, addresses, and/or data across a corresponding plurality of serialized communication link interfaces (SCLIs) between one or more originating devices or destination devices such as a processor and a switch. At the switch, one or more commands, addresses, or data corresponding to each stream can be transferred to a corresponding destination memory vault controller (MVC) associated with a corresponding memory vault. The destination MVC can perform write operations, read operations, and/or memory vault housekeeping operations independently from concurrent operations associated with other MVCs coupled to a corresponding plurality of memory vaults.
摘要翻译：本文公开的系统和方法基本上同时传送跨越一个或多个发起设备或诸如处理器和交换机的目的地设备之间的对应多个串行化通信链路接口（SCLI）的多个命令，地址和/或数据流。在交换机上，可以将与每个流相对应的一个或多个命令，地址或数据传送到与对应的存储器保险库相关联的对应的目的地存储器保管库控制器（MVC）。目的地MVC可以独立于与耦合到对应的多个存储器库的其他MVC相关联的并行操作执行写入操作，读取操作和/或存储器保管库内务处理操作。

9. 发明申请

US20120320688A1 SWITCHED INTERFACE STACKED-DIE MEMORY ARCHITECTURE 有权
标题翻译：切换界面堆叠式存储器架构
公开(公告)号：US20120320688A1
公开(公告)日：2012-12-20
申请号：US13595294
申请日：2012-08-27
申请人： Joe M. Jeddeloh , Paul A. LaBerge
发明人： Joe M. Jeddeloh , Paul A. LaBerge
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/76 , G06F13/1668 , G06F13/4239 , G11C5/02 , G11C7/10 , G11C8/10 , G11C29/04 , Y02B70/123 , Y02B70/126 , Y02D10/14 , Y02D10/151
摘要： Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request directly to an address decoder associated with a stacked-die memory vault without knowing whether a repair address is required. If a subsequent analysis of the memory request shows that a repair address is required, an in-process decode of the requested memory address can be halted and decoding of the repair address initiated.
摘要翻译：本文公开的系统和方法包括可以接收包括所请求的存储器地址的存储器请求的那些，并且可以将存储器请求直接发送到与堆叠的存储器存储库相关联的地址解码器，而不知道是否需要修复地址。如果对存储器请求的后续分析显示需要修复地址，则可以暂停所请求的存储器地址的进程内解码并启动修复地址的解码。

10. 发明申请

US20110264858A1 MULTI-SERIAL INTERFACE STACKED-DIE MEMORY ARCHITECTURE 有权
标题翻译：多串行接口堆叠存储器架构
公开(公告)号：US20110264858A1
公开(公告)日：2011-10-27
申请号：US13179156
申请日：2011-07-08
申请人： Joe M. Jeddeloh , Paul A. LaBerge
发明人： Joe M. Jeddeloh , Paul A. LaBerge
IPC分类号： G06F12/08
CPC分类号： G06F13/1668 , G06F13/1684 , G06F13/4022 , G06F2213/16 , Y02D10/14 , Y02D10/151
摘要： Systems and methods disclosed herein substantially concurrently transfer a plurality of streams of commands, addresses, and/or data across a corresponding plurality of serialized communication link interfaces (SCLIs) between one or more originating devices or destination devices such as a processor and a switch. At the switch, one or more commands, addresses, or data corresponding to each stream can be transferred to a corresponding destination memory vault controller (MVC) associated with a corresponding memory vault. The destination MVC can perform write operations, read operations, and/or memory vault housekeeping operations independently from concurrent operations associated with other MVCs coupled to a corresponding plurality of memory vaults.
摘要翻译：本文公开的系统和方法基本上同时传送跨越一个或多个发起设备或诸如处理器和交换机的目的地设备之间的对应多个串行化通信链路接口（SCLI）的多个命令，地址和/或数据流。在交换机上，可以将与每个流相对应的一个或多个命令，地址或数据传送到与对应的存储器保险库相关联的对应的目的地存储器保管库控制器（MVC）。目的地MVC可以独立于与耦合到对应的多个存储器库的其他MVC相关联的并行操作执行写入操作，读取操作和/或存储器保管库内务处理操作。

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