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1. 发明授权

US07633552B2 Self-calibrating timing circuits for use in a sync separator 失效
标题翻译：用于同步分离器的自校准定时电路
公开(公告)号：US07633552B2
公开(公告)日：2009-12-15
申请号：US12176893
申请日：2008-07-21
申请人： Zhinan (Peter) Wei , Robert David Zucker
发明人： Zhinan (Peter) Wei , Robert David Zucker
IPC分类号： H04N5/08
CPC分类号： H04N5/08 , H04N5/46 , H04N9/641
摘要： Provided herein are self-calibrating timing circuits and methods for use in a sync separator. A comparator compares a video signal to a video reference voltage to produce a sliced sync signal that has a frequency that is equal to a scan frequency of a horizontal sync embedded in the video signal. A first converter converts the sliced sync signal to a control signal having an amplitude or magnitude that is inversely proportional to the scan period of the horizontal sync embedded the video signal. A second converter converts the voltage control signal to a timer signal that has timed intervals that are that are inversely proportional to the amplitude or magnitude of the control signal, and thus proportional to the scan period of the horizontal sync embedded in the video signal. These timed intervals produced in accordance with embodiments of the present invention are easily and precisely scalable, allowing them to be used to discriminate various timing features embedded in video signals. This abstract is not intended to be a complete description of, or limit the scope of, the invention.
摘要翻译：本文提供了用于同步分离器的自校准定时电路和方法。比较器将视频信号与视频参考电压进行比较，以产生具有等于嵌入在视频信号中的水平同步的扫描频率的频率的分片同步信号。第一转换器将切片的同步信号转换成具有与嵌入视频信号的水平同步的扫描周期成反比的幅度或幅度的控制信号。第二转换器将电压控制信号转换成具有与控制信号的幅度或幅度成反比的定时间隔的定时器信号，并且因此与嵌入在视频信号中的水平同步的扫描周期成比例。根据本发明的实施例产生的这些定时间隔容易且精确地可扩展，允许它们用于区分嵌入在视频信号中的各种定时特征。本摘要不是对本发明的完整描述或限制本发明的范围。

2. 发明申请

US20080278625A1 SELF-CALIBRATING TIMING CIRCUITS FOR USE IN A SYNC SEPARATOR 失效
标题翻译：用于同步分离器的自校准时序电路
公开(公告)号：US20080278625A1
公开(公告)日：2008-11-13
申请号：US12176893
申请日：2008-07-21
申请人： Zhinan (Peter) Wei , Robert David Zucker
发明人： Zhinan (Peter) Wei , Robert David Zucker
IPC分类号： H04N5/04
CPC分类号： H04N5/08 , H04N5/46 , H04N9/641
摘要： Provided herein are self-calibrating timing circuits and methods for use in a sync separator. A comparator compares a video signal to a video reference voltage to produce a sliced sync signal that has a frequency that is equal to a scan frequency of a horizontal sync embedded in the video signal. A first converter converts the sliced sync signal to a control signal having an amplitude or magnitude that is inversely proportional to the scan period of the horizontal sync embedded the video signal. A second converter converts the voltage control signal to a timer signal that has timed intervals that are that are inversely proportional to the amplitude or magnitude of the control signal, and thus proportional to the scan period of the horizontal sync embedded in the video signal. These timed intervals produced in accordance with embodiments of the present invention are easily and precisely scalable, allowing them to be used to discriminate various timing features embedded in video signals. This abstract is not intended to be a complete description of, or limit the scope of, the invention.
摘要翻译：本文提供了用于同步分离器的自校准定时电路和方法。比较器将视频信号与视频参考电压进行比较，以产生具有等于嵌入在视频信号中的水平同步的扫描频率的频率的分片同步信号。第一转换器将切片的同步信号转换成具有与嵌入视频信号的水平同步的扫描周期成反比的幅度或幅度的控制信号。第二转换器将电压控制信号转换成具有与控制信号的幅度或幅度成反比的定时间隔的定时器信号，并且因此与嵌入在视频信号中的水平同步的扫描周期成比例。根据本发明的实施例产生的这些定时间隔容易且精确地可扩展，允许它们用于区分嵌入在视频信号中的各种定时特征。本摘要不是对本发明的完整描述或限制本发明的范围。

3. 发明授权

US07423694B2 Self-calibrating timing circuits for use in a sync separator 有权
标题翻译：用于同步分离器的自校准定时电路
公开(公告)号：US07423694B2
公开(公告)日：2008-09-09
申请号：US11201065
申请日：2005-08-09
申请人： Zhinan (Peter) Wei , Robert David Zucker
发明人： Zhinan (Peter) Wei , Robert David Zucker
IPC分类号： H04N5/08
CPC分类号： H04N5/08 , H04N5/46 , H04N9/641
摘要： Provided herein are self-calibrating timing circuits and methods for use in a sync separator. A comparator compares a video signal to a video reference voltage to produce a sliced sync signal that has a frequency that is equal to a scan frequency of a horizontal sync embedded in the video signal. A frequency-to-voltage converter converts the sliced sync signal to a voltage control signal having an amplitude that is inversely proportional to the scan period of the horizontal sync embedded the video signal. A voltage-to-timed interval converter that converts the voltage control signal to a timer signal that has timed intervals that are that are inversely proportional to the amplitude of the voltage control signal, and thus proportional to the scan period of the horizontal sync embedded in the video signal. These timed intervals produced in accordance with embodiments of the present invention are easily and precisely scalable, allowing them to be used to discriminate various timing features embedded in video signals. This abstract is not intended to be a complete description of, or limit the scope of, the invention.
摘要翻译：本文提供了用于同步分离器的自校准定时电路和方法。比较器将视频信号与视频参考电压进行比较，以产生具有等于嵌入在视频信号中的水平同步的扫描频率的频率的分片同步信号。频率 - 电压转换器将切片的同步信号转换成具有与嵌入视频信号的水平同步的扫描周期成反比的幅度的电压控制信号。一种电压 - 定时间隔转换器，其将电压控制信号转换成具有与电压控制信号的幅度成反比的定时间隔的定时器信号，并且因此与嵌入在电平控制信号中的水平同步的扫描周期成正比视频信号。根据本发明的实施例产生的这些定时间隔容易且精确地可扩展，允许它们用于区分嵌入在视频信号中的各种定时特征。本摘要不是对本发明的完整描述或限制本发明的范围。

4. 发明授权

US06781532B2 Simplified multi-output digital to analog converter (DAC) for a flat panel display 失效
标题翻译：用于平板显示器的简化多输出数模转换器（DAC）
公开(公告)号：US06781532B2
公开(公告)日：2004-08-24
申请号：US10236211
申请日：2002-09-05
申请人： Zhinan (Peter) Wei
发明人： Zhinan (Peter) Wei
IPC分类号： H03M100
CPC分类号： H03M1/662 , G09G3/3696
摘要： A method and apparatus for generating reference voltages for a flat panel display system using a digital to analog converter (DAC) to supply multiple reference voltages to the flat panel display system. The DAC is adapted to accept digital input voltage reference from one of a plurality of registers and to provide an analog output to one of a plurality of sample and hold circuits. A controller selects which one of the plurality of registers is coupled to the DAC input, and selects which one of the plurality of sample and hold circuits is coupled to the DAC output.
摘要翻译：一种用于为使用数模转换器（DAC）向平板显示系统提供多个参考电压的平板显示系统产生参考电压的方法和装置。 DAC适于从多个寄存器之一接收数字输入电压基准，并向多个采样和保持电路之一提供模拟输出。控制器选择多个寄存器中的哪一个耦合到DAC输入，并选择多个采样和保持电路中的哪一个耦合到DAC输出。

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