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    • 8. 发明授权
    • Device having multiplexer for enabling priority and non-priority common
circuit
    • 具有用于使能优先级和非优先级公共电路的多路复用器的装置
    • US4872108A
    • 1989-10-03
    • US159817
    • 1988-02-24
    • Andre BussonniereYves Courtois
    • Andre BussonniereYves Courtois
    • G06F15/16G06F9/52G06F13/18G06F15/177
    • G06F13/18
    • A priority processor (1) and a non-priority processor (20) cooperatively access a common memory (30) by means of an address multiplexer (40) which memory and multiplexer are controlled by a control unit (60). The priority processor issues data strobe (DSSN), clock (CLK) and write control (WSN) signals to the control unit to which the non-polarity processor also issues various memory access request signals. By forming a preparation signal (DSSN=0), the priority processor, through the control unit, claims the memory for a memory access cycle if a prior memory access request by the non-priority processor occurred less than about a clock cycle earlier.
    • 优先处理器(1)和非优先处理器(20)通过地址多路复用器(40)协同地访问公共存储器(30),所述存储器和多路复用器由控制单元(60)控制。 优先处理器向非极性处理器也发出各种存储器访问请求信号的控制单元发出数据选通(DSSN),时钟(CLK)和写入控制(WSN)信号。 通过形成准备信号(DSSN = 0),如果非优先处理器的先前存储器访问请求发生时间小于大约一个时钟周期,则通过控制单元的优先处理器要求存储器进行存储器访问周期。