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1. 发明授权

US06230291B1 Microcomputer including burn-in test circuit and burn-in test method thereof including mode switching device 有权
标题翻译：微型计算机包括老化测试电路及其老化试验方法，包括模式切换装置
公开(公告)号：US06230291B1
公开(公告)日：2001-05-08
申请号：US09143241
申请日：1998-08-28
申请人： Yusuke Tokieda
发明人： Yusuke Tokieda
IPC分类号： G11C2900
CPC分类号： G06F11/2236 , G06F11/22 , G06F11/2273
摘要： This invention discloses a microcomputer and a method of its burn-in test in which the burn-in test for detecting the initial defects of the parts necessary to detect the defects of the microcomputer is carried out while keeping the microcomputer mounted on the same burn-in test device. When a burn-in test mode signal is activated by a mode decoder, a mode switching circuit carries out switching so as to activate either one of a ROM dump mode signal or a test ROM execution signal, by means of a mode switching signal from a mode switching terminal. A central processing unit dumps data of the user ROM when the ROM dump mode signal is activated, and executes a program stored in the test ROM when the test ROM execution signal is activated, to gain access to various parts of the microcomputer. A reset signal is used as the mode switching signal.
摘要翻译：本发明公开了一种微型计算机及其老化测试方法，其中，在将微型计算机安装在同一燃烧室上的同时进行用于检测检测微型计算机缺陷所必需的部件的初始缺陷的老化试验，在测试设备中。当模式解码器激活老化测试模式信号时，模式切换电路通过来自模拟解码器的模式切换信号执行切换以便激活ROM转储模式信号或测试ROM执行信号中的任一个模式切换端子。当ROM转储模式信号被激活时，中央处理单元转储用户ROM的数据，并且当测试ROM执行信号被激活时执行存储在测试ROM中的程序，以访问微型计算机的各个部分。复位信号用作模式切换信号。

2. 发明授权

US5771361A Data processor having shared terminal for monitoring internal and external memory events 失效
标题翻译：具有用于监视内部和外部存储器事件的共享终端的数据处理器
公开(公告)号：US5771361A
公开(公告)日：1998-06-23
申请号：US490447
申请日：1995-06-14
申请人： Yusuke Tokieda , Hiroshi Katsuta
发明人： Yusuke Tokieda , Hiroshi Katsuta
IPC分类号： G06F11/28 , G06F11/36 , G06F15/78 , G06F13/00
CPC分类号： G06F11/3656 , G06F11/364
摘要： In a data processor, an internal memory stores instruction codes and a central processing unit reads an instruction code form the memory and produces an external access request if it contains an instruction to access an external memory which is connected to an external terminal. A bus controller is responsive to the request for producing a data timing signal and one of read and write signals. An external address bus and an external data bus are connected to the bus controller. An internal address bus is connected to the CPU for transporting an internal address signal. A selecting circuit is responsive to a first mode switching signal for coupling one of the external address bus and the external data bus to the external terminal and determining the direction of the data signal transported by the external data bus when it is coupled to the external terminal in accordance with the data timing signal and one of the read and write signals, and responsive to a second mode switching signal for coupling the internal address bus to the external terminal in the absence of the data timing signal and the read and write signals. For an external memory having separate data and address terminals, a second external terminal is additionally provided for coupling the external address bus direct to the address terminal of the external memory through the second external terminal, instead of through the selecting circuit.
摘要翻译：在数据处理器中，内部存储器存储指令代码，并且中央处理单元从存储器读取指令代码，并且如果其包含访问连接到外部端子的外部存储器的指令，则产生外部访问请求。总线控制器响应于产生数据定时信号和读取和写入信号之一的请求。外部地址总线和外部数据总线连接到总线控制器。内部地址总线连接到CPU，用于传送内部地址信号。选择电路响应于第一模式切换信号，用于将外部地址总线和外部数据总线中的一个耦合到外部端子，并且当外部数据总线耦合到外部端子时确定由外部数据总线传输的数据信号的方向根据数据定时信号和读取和写入信号之一，并且响应于在不存在数据定时信号和读取和写入信号的情况下将内部地址总线耦合到外部端子的第二模式切换信号。对于具有单独的数据和地址端子的外部存储器，另外提供第二外部端子，用于通过第二外部端子将外部地址总线直接耦合到外部存储器的地址端子，而不是通过选择电路。

3. 发明授权

US5511013A Low power consumption type one-chip microcomputer having a plurality of peripheral circuits 失效
标题翻译：具有多个外围电路的低功耗型单片机
公开(公告)号：US5511013A
公开(公告)日：1996-04-23
申请号：US274004
申请日：1994-07-12
申请人： Yusuke Tokieda , Hiroshi Katsuta
发明人： Yusuke Tokieda , Hiroshi Katsuta
IPC分类号： G06F1/04 , G06F1/32 , G06F15/78 , G06F1/00
CPC分类号： G06F1/3215 , G06F1/325
摘要： A microcomputer includes a plurality of peripheral circuits accessed by a central processing unit for a reading/writing of the peripheral circuits. Each of the external terminals supplies a selection signal indicative of use or non-use of a corresponding peripheral circuit. Each selection signal is supplied to a gate circuit provided for the corresponding peripheral circuit, for controlling permission and inhibition of application of a clock signal or a strobe signal to the corresponding peripheral circuit. Thus, neither the clock nor the strobe signal is supplied to the peripheral circuits which are not used in an actual application system, with the result that a low power consumption, highly reliable microcomputer is realized.
摘要翻译：微型计算机包括由中央处理单元访问的用于外围电路的读/写的多个外围电路。每个外部端子提供指示使用或不使用相应的外围电路的选择信号。每个选择信号被提供给为对应的外围电路提供的门电路，用于控制对相应的外围电路施加时钟信号或选通信号的许可和禁止。因此，时钟和选通信号都不被提供给实际应用系统中未使用的外围电路，结果实现了低功耗，高可靠性的微计算机。

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