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1. 发明申请

US20100325360A1 MULTI-CORE PROCESSOR AND MULTI-CORE PROCESSOR SYSTEM 审中-公开
标题翻译：多核处理器和多核处理器系统
公开(公告)号：US20100325360A1
公开(公告)日：2010-12-23
申请号：US12813567
申请日：2010-06-11
申请人： Yumi Yoshitake , Shunsuke Sasaki
发明人： Yumi Yoshitake , Shunsuke Sasaki
IPC分类号： G06F12/08
CPC分类号： G06F12/0223 , G06F12/0817
摘要： In one embodiment, a multi-core processor includes a plurality of processor cores that each includes a cache and that uses a management target area allocated as a main memory in a memory area. The multi-core processor includes a state managing unit and a management-target-area. The state managing unit manages a first state in which the small area is not allocated to the processor core and a second state in which the small area is allocated to the processor core for each small area included in the management target area. The management-target-area increasing and decreasing unit increases and decreases the management target area by increasing and decreasing the small area in the first state in the management target area.
摘要翻译：在一个实施例中，多核处理器包括多个处理器核，每个处理器核包括高速缓存，并且使用在存储器区域中分配为主存储器的管理目标区域。多核处理器包括状态管理单元和管理目标区域。状态管理单元管理小区域未分配给处理器核心的第一状态以及其中小区域被分配给管理目标区域中包括的每个小区域的处理器核心的第二状态。管理目标区域增减单位通过增加和减少管理对象区域的第一状态的小区域来增加和减少管理目标区域。

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