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1. 发明授权

US08804225B2 Signal shaping circuit and light transmitting device 有权
标题翻译：信号整形电路和发光装置
公开(公告)号：US08804225B2
公开(公告)日：2014-08-12
申请号：US13566542
申请日：2012-08-03
申请人： Yukito Tsunoda
发明人： Yukito Tsunoda
IPC分类号： G02F1/03 , H03H15/00
CPC分类号： H03H15/00
摘要： A signal shaping circuit includes an operational circuit that provides weights to a first signal input to a first input element and a second signal input to a second input element, adds or subtracts the second signal to or from the first signal, and outputs a signal obtained by adding or subtracting the second signal to or from the first signal; a divider that divides the signal output from the operational circuit into signals, causes one of the divided signal to be input to the second input element, and outputs the other of the divided signal; a delay element that delays the signal output from the operational circuit and to be input to the divider or the signal output from the divider and to be input to the second input element; and an adjuster that adjusts at least one of the weights provided to the first and second signals.
摘要翻译：信号整形电路包括对输入到第一输入元件的第一信号和输入到第二输入元件的第二信号提供权重的运算电路，对第一信号进行加法或减法，并输出获得的信号通过向第一信号加上或从第一信号减去第二信号; 将从运算电路输出的信号分割为信号的分频器，将分频信号中的一个输入到第二输入单元，输出另一个分频信号; 延迟元件，其延迟从操作电路输出的信号并将其输入到分频器或从分频器输出的信号并输入到第二输入元件; 以及调节器，其调整提供给所述第一和第二信号的权重中的至少一个权重。

2. 发明授权

US08630369B2 Emphasis circuit and transmitter 有权
标题翻译：强调电路和变送器
公开(公告)号：US08630369B2
公开(公告)日：2014-01-14
申请号：US13609562
申请日：2012-09-11
申请人： Yukito Tsunoda
发明人： Yukito Tsunoda
IPC分类号： H04L25/03 , H04L25/49
CPC分类号： H04L25/0286
摘要： An emphasis circuit includes: an applying circuit to add an emphasis signal to an input differential signal; a feedback path to feed back a differential output of the applying unit; a comparing circuit to compare a direct current component level of a positive phase signal and of a negative phase signal of the differential signal; a direct current component level controlling circuit to control a direct current component level of at least one of the positive phase signal and the negative phase signal; a delay unit circuit to add a delay to at least one of the fed-backed differential signal to generate the emphasis signal and inputs the emphasis signal into the applying unit; and a dummy load coupled to a positive phase signal output or a negative phase signal output of the applying unit.
摘要翻译：强调电路包括：施加电路，用于将加重信号加到输入差分信号上; 用于反馈施加单元的差分输出的反馈路径; 比较电路，用于比较正相信号和差分信号的负相位信号的直流分量电平; 直流分量电平控制电路，用于控制正相信号和负相位信号中的至少一个的直流分量电平; 延迟单元电路，用于向所述反馈差分信号中的至少一个增加延迟以产生所述加重信号，并将所述加重信号输入到所述施加单元中; 以及耦合到施加单元的正相位信号输出或负相位信号输出的虚拟负载。

3. 发明授权

US08478138B2 Optical receiving device, optical receiving circuit, and method for receiving optical signals 有权
标题翻译：光接收装置，光接收电路和接收光信号的方法
公开(公告)号：US08478138B2
公开(公告)日：2013-07-02
申请号：US12623548
申请日：2009-11-23
申请人： Mariko Sugawara , Yukito Tsunoda , Satoshi Ide
发明人： Mariko Sugawara , Yukito Tsunoda , Satoshi Ide
IPC分类号： H04B10/06
CPC分类号： H04B10/677
摘要： There is provided an optical receiving device for deriving a signal using for data identification. The optical receiving device includes a demodulator for demodulating a modulated optical signal to an demodulated optical signal, a convertor for converting the demodulated optical signal to a first and a second electric signals, a generator for generating a complement signal by summing the first electric signal of a normal in phase component and the second electric signal of a reverse in phase component, and a suppressor for suppressing, by the use of the complement signal, a variation of potential which appears in a data signal at a time of phase changing of the modulated optical signal, the data signal being a difference of the normal in phase component and the reverse in phase component.
摘要翻译：提供了一种用于导出用于数据识别的信号的光学接收装置。光接收装置包括用于将经调制的光信号解调为解调的光信号的解调器，用于将解调的光信号转换为第一和第二电信号的转换器，用于通过将第一电信号正相位分量和反相位分量的第二电信号，以及抑制器，用于通过使用补码信号来抑制在调制的相位变化时在数据信号中出现的电位变化光信号，数据信号是正相同步分量和反相相位分量的差。

4. 发明申请

US20130077149A1 SIGNAL SHAPING CIRCUIT AND LIGHT TRANSMITTING DEVICE 有权
标题翻译：信号形成电路和发光装置
公开(公告)号：US20130077149A1
公开(公告)日：2013-03-28
申请号：US13566542
申请日：2012-08-03
申请人： Yukito TSUNODA
发明人： Yukito TSUNODA
IPC分类号： H03H11/26 , G02F1/01
CPC分类号： H03H15/00
摘要： A signal shaping circuit includes an operational circuit that provides weights to a first signal input to a first input element and a second signal input to a second input element, adds or subtracts the second signal to or from the first signal, and outputs a signal obtained by adding or subtracting the second signal to or from the first signal; a divider that divides the signal output from the operational circuit into signals, causes one of the divided signal to be input to the second input element, and outputs the other of the divided signal; a delay element that delays the signal output from the operational circuit and to be input to the divider or the signal output from the divider and to be input to the second input element; and an adjuster that adjusts at least one of the weights provided to the first and second signals.
摘要翻译：信号整形电路包括对输入到第一输入元件的第一信号和输入到第二输入元件的第二信号提供权重的运算电路，对第一信号进行加法或减法，并输出获得的信号通过向第一信号加上或从第一信号减去第二信号; 将从运算电路输出的信号分割为信号的分频器，将分频信号中的一个输入到第二输入单元，输出另一个分频信号; 延迟元件，其延迟从操作电路输出的信号并将其输入到分频器或从分频器输出的信号并输入到第二输入元件; 以及调节器，其调整提供给所述第一和第二信号的权重中的至少一个权重。

5. 发明授权

US08306437B2 Optical receiver 失效
标题翻译：光接收机
公开(公告)号：US08306437B2
公开(公告)日：2012-11-06
申请号：US12457052
申请日：2009-05-29
申请人： Yukito Tsunoda , Satoshi Ide , Shinichi Sakuramoto , Kazuyuki Mori , Toru Matsuyama
发明人： Yukito Tsunoda , Satoshi Ide , Shinichi Sakuramoto , Kazuyuki Mori , Toru Matsuyama
IPC分类号： H04B10/06
CPC分类号： H04B10/6931 , H01L31/02027 , H04B10/6911
摘要： In an optical receiver, a light receiving element receives the optical packet signals and converts the optical packet signals to electrical signals. A bias voltage supply section supplies bias voltage to the light receiving element. A monitoring section monitors an input level of each optical packet signal or each electrical signal and transmits a monitored value to the bias voltage supply section. In addition, the bias voltage supply section temporarily increases the bias voltage according to magnitude of the monitored value after an end of receiving of each optical packet signal.
摘要翻译：在光接收器中，光接收元件接收光分组信号，并将光分组信号转换为电信号。偏置电压供应部分向受光元件提供偏置电压。监视部分监视每个光分组信号或每个电信号的输入电平，并将监测值发送到偏置电压提供部分。此外，偏置电压提供部分在每个光分组信号的接收结束之后根据监视值的大小暂时增加偏置电压。

6. 发明申请

US20120235727A1 SIGNAL SHAPING CIRCUIT 有权
标题翻译：信号形状电路
公开(公告)号：US20120235727A1
公开(公告)日：2012-09-20
申请号：US13330299
申请日：2011-12-19
申请人： Hideki OKU , Yukito Tsunoda
发明人： Hideki OKU , Yukito Tsunoda
IPC分类号： H03L5/00
CPC分类号： H04B10/504 , H01S5/0428 , H01S5/06216 , H01S5/183
摘要： A signal shaping circuit that shapes a drive signal and includes a main-signal amplifying circuit that amplifies the drive signal; a preemphasis generating circuit that symmetrically emphasizes a rising portion and a falling portion of the drive signal; a current source that is provided in the main-signal amplifying circuit; and a condenser that couples the main-signal amplifying circuit and the preemphasis generating circuit.
摘要翻译：信号整形电路，其对驱动信号进行整形，并包括放大驱动信号的主信号放大电路; 预加重产生电路，其对称地强调驱动信号的上升部分和下降部分; 设置在主信号放大电路中的电流源; 以及耦合主信号放大电路和预加重产生电路的电容器。

7. 发明授权

US08169348B2 Parallel-serial converter circuit 有权
标题翻译：并行串行转换电路
公开(公告)号：US08169348B2
公开(公告)日：2012-05-01
申请号：US12907399
申请日：2010-10-19
申请人： Yukito Tsunoda
发明人： Yukito Tsunoda
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： In a parallel-serial converter circuit of a multistage configuration, there is formed a clock propagation path so that when multistage connected data converters are operated according to the timing of a clock signal, a reference clock signal or a clock signal in which the reference clock signal has been frequency-converted, is given sequentially to the data converter of the first stage up to the data converter of the final stage. As a result, even in a case where variations occur in power supply voltage, timing deviation of data signals and clock signals input to the data converters of the second and subsequent stages can be suppressed, and parallel-serial conversion of high-speed data signals can be reliably executed.
摘要翻译：在多级配置的并行串行转换器电路中，形成时钟传播路径，使得当根据时钟信号的时序，参考时钟信号或时钟信号来操作多级连接的数据转换器时，其中参考时钟信号已被频率转换，被顺序地提供给第一级的数据转换器直到最终级的数据转换器。结果，即使在电源电压发生变化的情况下，可以抑制输入到第二级和后级的数据转换器的数据信号和时钟信号的定时偏差，并且还可以并行串行转换高速数据信号可以可靠地执行。

8. 发明授权

US08126328B2 Communication apparatus and signal transmitting method 有权
标题翻译：通信设备和信号传输方法
公开(公告)号：US08126328B2
公开(公告)日：2012-02-28
申请号：US12320795
申请日：2009-02-04
申请人： Yukito Tsunoda
发明人： Yukito Tsunoda
IPC分类号： H04J4/00 , H04J14/08
CPC分类号： H04J3/1694 , H04J7/00 , H04L7/065 , H04L25/4902 , H04Q2011/0064
摘要： A communication apparatus time-division multiplexes a first signal transmitted at a first bit rate and a second signal transmitted at a second bit rate which is an integer multiple of the first bit rate, and sends out the first signal and the second signal to one line. The communication apparatus includes a pulse generating unit and a pulse superimposing unit. The pulse generating unit generates repetitive pulses having a width equal to a width of the first signal. The pulse superimposing unit superimposes the pulses generated by the pulse generating unit on the second signal.
摘要翻译：通信装置对以第一比特率发送的第一信号和以第一比特率的整数倍的第二比特率发送的第二信号进行时分复用，并将第一信号和第二信号发送到一行。通信装置包括脉冲发生单元和脉冲叠加单元。脉冲发生单元产生宽度等于第一信号的宽度的重复脉冲。脉冲叠加单元将由脉冲发生单元生成的脉冲叠加在第二信号上。

9. 发明申请

US20110181451A1 PARALLEL-SERIAL CONVERTER 有权
标题翻译：并联串行转换器
公开(公告)号：US20110181451A1
公开(公告)日：2011-07-28
申请号：US12985782
申请日：2011-01-06
申请人： Yukito Tsunoda
发明人： Yukito Tsunoda
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： A parallel-serial converter includes a converter circuit that converts parallel data into serial data; a first sampling circuit that samples, according to a first clock signal, the serial data output from the converter circuit; a second sampling circuit that samples, according to a second clock signal that is an inverse of the first clock signal, replica data that is synchronized with the serial data; a third sampling circuit that samples, according to plural third signals respectively having different phases, output from the second sampling circuit; and a control circuit that controls sampling timing of the first sampling circuit, based on each output from the third sampling circuit.
摘要翻译：并行串行转换器包括将并行数据转换为串行数据的转换器电路; 第一采样电路，根据第一时钟信号对从转换器电路输出的串行数据进行采样; 第二采样电路，根据与所述第一时钟信号相反的第二时钟信号，与所述串行数据同步的复制数据进行采样; 第三采样电路，根据分别具有不同相位的多个第三信号从第二采样电路输出; 以及控制电路，其基于来自第三采样电路的每个输出来控制第一采样电路的采样定时。

10. 发明申请

US20110122002A1 PARALLEL-SERIAL CONVERTER CIRCUIT 有权
标题翻译：并联串行转换器电路
公开(公告)号：US20110122002A1
公开(公告)日：2011-05-26
申请号：US12907399
申请日：2010-10-19
申请人： Yukito TSUNODA
发明人： Yukito TSUNODA
IPC分类号： H03M9/00 , H03L7/00
CPC分类号： H03M9/00
摘要： In a parallel-serial converter circuit of a multistage configuration, there is formed a clock propagation path so that when multistage connected data converters are operated according to the timing of a clock signal, a reference clock signal or a clock signal in which the reference clock signal has been frequency-converted, is given sequentially to the data converter of the first stage up to the data converter of the final stage. As a result, even in a case where variations occur in power supply voltage, timing deviation of data signals and clock signals input to the data converters of the second and subsequent stages can be suppressed, and parallel-serial conversion of high-speed data signals can be reliably executed.
摘要翻译：在多级配置的并行串行转换器电路中，形成时钟传播路径，使得当根据时钟信号的时序，参考时钟信号或时钟信号来操作多级连接的数据转换器时，其中参考时钟信号已被频率转换，被顺序地提供给第一级的数据转换器直到最终级的数据转换器。结果，即使在电源电压发生变化的情况下，可以抑制输入到第二级和后级的数据转换器的数据信号和时钟信号的定时偏差，并且还可以并行串行转换高速数据信号可以可靠地执行。

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