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1. 发明申请

US20120148947A1 DEVELOPER, DEVELOPER CONTAINER, IMAGE FORMING UNIT AND IMAGE FORMING APPARATUS 审中-公开
标题翻译：开发商，开发商容器，图像形成单元和图像形成装置
公开(公告)号：US20120148947A1
公开(公告)日：2012-06-14
申请号：US13313617
申请日：2011-12-07
申请人： Yuki MATSUURA
发明人： Yuki MATSUURA
IPC分类号： G03G9/00 , G03G15/08
CPC分类号： G03G9/0823 , G03G9/0806 , G03G9/0821 , G03G9/08711 , G03G9/08755 , G03G2215/0614 , G03G2215/0617
摘要： Disclosed is a developer including at least a toner for developing electrostatic latent images. The toner includes toner base particles each containing at least one binder resin, and external additives for adhering to the outer surfaces of the toner base particles. The toner has a first triboelectric charge obtained by blow-off charge measurement at 20% relative humidity and a temperature of 10° C., and a second triboelectric charge obtained by blow-off charge measurement at 80% relative humidity and a temperature of 28° C. An absolute value of the difference between the first and second triboelectric charges is no larger than 20 μC/g.
摘要翻译：公开了一种显影剂，其至少包括用于显影静电潜像的调色剂。调色剂包括各自含有至少一种粘合剂树脂的调色剂基础颗粒和用于粘附到调色剂基础颗粒的外表面的外部添加剂。调色剂具有通过在20％相对湿度和10℃的温度下进行吹离电荷测量获得的第一摩擦电荷，以及在80％相对湿度和28度温度下通过吹扫电荷测量获得的第二摩擦电荷第一和第二摩擦电荷之间的差的绝对值不大于20μC/ g。

2. 发明授权

US5970368A Method for manufacturing polycrystal semiconductor film 失效
标题翻译：多晶半导体膜的制造方法
公开(公告)号：US5970368A
公开(公告)日：1999-10-19
申请号：US939660
申请日：1997-09-29
申请人： Hideyuki Sasaki , Michihiro Oose , Isao Suzuki , Shiro Takeno , Mitsuhiro Tomita , Yoshito Kawakyu , Yuki Matsuura , Hiroshi Mitsuhashi
发明人： Hideyuki Sasaki , Michihiro Oose , Isao Suzuki , Shiro Takeno , Mitsuhiro Tomita , Yoshito Kawakyu , Yuki Matsuura , Hiroshi Mitsuhashi
IPC分类号： H01L21/20 , H01L21/205 , H01L29/04
CPC分类号： H01L21/2026
摘要： There is disclosed a method for manufacturing a polycrystal semiconductor film comprising the steps of applying a high energy beam to a surface of a semiconductor film comprising an amorphous or a polycrystal semiconductor provided on a surface of a substrate to melt only the semiconductor film, and solidifying the film via a solid and liquid coexisting state to form a semiconductor film comprising a polycrystal semiconductor having a large grain diameter, by heating a liquid part using a difference in an electric resistance in the liquid and solid coexisting state to heat only the liquid part, and by extending the solidification time until the completion of solidifying of the molten liquid crystal film. Furthermore, as the base film of the semiconductor film, a material having a melting point of 1600.degree. C. and a thermal conductivity of 0.01 cal/cm.s..degree. C. is used to suppress heat dissipation from the molten liquid of the semiconductor to the substrate so that time until the complete solidification can be prolonged. Furthermore, the beam is irradiated so as to form a standing wave at a predetermined position of the surface of the semiconductor film to generate the heat density distribution having the same cycle with the standing wave and to melt the semiconductor film with the result that a polycrystal semiconductor film comprising a uniform and a large crystal grains by controlling the distribution of the crystal nuclei at the interface between the base film and the substrate.
摘要翻译：公开了一种制造多晶半导体膜的方法，包括以下步骤：将高能束施加到包括设置在基板表面上的非晶或多晶半导体的半导体膜的表面，以仅熔化半导体膜，并固化通过固体和液体共存状态形成包含具有大粒径的多晶半导体的半导体膜，通过使用液体中的电阻差和固体共存状态加热液体部分以仅加热液体部分，并延长凝固时间直到熔融液晶膜凝固完成。此外，作为半导体膜的基膜，具有熔点为1600℃，导热率为0.01cal / cm 3的材料。使用DEG来抑制从半导体的熔融液体到基板的散热，从而可以延长直到完全凝固的时间。此外，照射光束以在半导体膜的表面的预定位置处形成驻波，以产生具有与驻波相同周期的热密度分布并熔化半导体膜，结果是多晶通过控制在基膜和基板之间的界面处的晶核的分布而包含均匀和大的晶粒的半导体膜。

3. 发明授权

US5356708A Insulated wire 失效
标题翻译：绝缘电线
公开(公告)号：US5356708A
公开(公告)日：1994-10-18
申请号：US978975
申请日：1992-11-23
申请人： Yuki Matsuura , Isao Ueoka , Koichi Iwata
发明人： Yuki Matsuura , Isao Ueoka , Koichi Iwata
IPC分类号： C08G18/34 , C08G18/76 , C08G73/14 , C09D179/08 , H01B3/30 , H01B3/18
CPC分类号： H01B3/306 , C08G18/345 , C08G18/7685 , C08G73/14 , C09D179/08 , Y10T428/2933 , Y10T428/294 , Y10T428/2942 , Y10T428/2947 , Y10T428/31681
摘要： An insulated wire comprising a conductor and an insulating coating made from a polyamideimide base coating, which polyamideimide is made of an acid component and a diisocyanate component containing 10 to 80 % by mole of an aromatic diisocyanate compound of the formula: ##STR1## or which polyamideimide is made of an diisocyanate component and an imidodicarboxylic acid that is a reaction product of an acid component and a diamine component, in which the diamine component contains an aromatic diamine compound of the formula: ##STR2## and/or the diisocyanate component contains the above aromatic diisocyanate compound in such an amount that a total amount of the aromatic diamine compound and the diisocyanate compound is from 10 to 80 % by mole based on the total amount of the whole diamine component and the whole diisocyanate component.
摘要翻译：一种绝缘线，其包括导体和由聚酰胺酰亚胺基底涂层制成的绝缘涂层，所述聚酰胺酰亚胺由酸组分和含有10至80摩尔％的下式的芳族二异氰酸酯化合物的二异氰酸酯组分：聚酰胺酰亚胺由二异氰酸酯组分和作为酸组分和二胺组分的反应产物的亚氨二羧酸制成，其中二胺组分含有下式的芳族二胺化合物：和/或二异氰酸酯组分含有芳香族二异氰酸酯化合物的含量相对于二胺成分和全部二异氰酸酯成分的总量相对于芳族二胺化合物和二异氰酸酯化合物的总量为10〜80摩尔％。

4. 发明申请

US20120199827A1 THIN-FILM TRANSISTOR CIRCUIT SUBSTRATE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：薄膜晶体管电路基板及其制造方法
公开(公告)号：US20120199827A1
公开(公告)日：2012-08-09
申请号：US13329545
申请日：2011-12-19
申请人： Tetsuya Shibata , Hajime Watakabe , Atsushi Sasaki , Yuki Matsuura , Muneharu Akiyoshi , Hiroyuki Watanabe
发明人： Tetsuya Shibata , Hajime Watakabe , Atsushi Sasaki , Yuki Matsuura , Muneharu Akiyoshi , Hiroyuki Watanabe
IPC分类号： H01L29/786 , H01L21/34
CPC分类号： H01L27/1225 , H01L29/66969 , H01L29/78606 , H01L29/7869
摘要： According to one embodiment, a method of manufacturing a thin-film transistor circuit substrate including forming an oxide semiconductor thin film above an insulative substrate, forming a gate insulation film and a gate electrode which are stacked on a first region of the oxide semiconductor thin film, and exposing from the gate insulation film a second region and a third region of the oxide semiconductor thin film, the second region and the third region being located on both sides of the first region of the oxide semiconductor thin film, forming an interlayer insulation film of silicon nitride including dangling bonds of silicon, the interlayer insulation film covering the second region and the third region of the oxide semiconductor thin film, the gate insulation film and the gate electrode, and forming a source electrode and a drain electrode.
摘要翻译：根据一个实施例，制造薄膜晶体管电路衬底的方法包括在绝缘衬底上形成氧化物半导体薄膜，形成栅极绝缘膜和栅电极，所述栅极绝缘膜和栅电极层叠在氧化物半导体薄膜的第一区域上并且从所述栅极绝缘膜暴露所述氧化物半导体薄膜的第二区域和第三区域，所述第二区域和所述第三区域位于所述氧化物半导体薄膜的所述第一区域的两侧，形成层间绝缘膜包括硅的悬挂键，覆盖第二区域的层间绝缘膜和氧化物半导体薄膜的第三区域，栅极绝缘膜和栅电极，以及形成源电极和漏电极。

5. 发明申请

US20120052432A1 DEVELOPER, DEVELOPMENT DEVICE, IMAGE FORMING DEVICE AND METHOD OF FORMING DEVELOPER 有权
标题翻译：开发者，开发设备，图像形成装置和形成开发者的方法
公开(公告)号：US20120052432A1
公开(公告)日：2012-03-01
申请号：US13221008
申请日：2011-08-30
申请人： Yuki MATSUURA
发明人： Yuki MATSUURA
IPC分类号： G03G9/00 , G03G15/08
CPC分类号： G03G21/1814 , G03G9/0827 , G03G9/09708 , G03G9/09725 , G03G9/09733 , G03G9/0975
摘要： A negatively chargeable developer includes: negatively chargeable toner mother particles including at least binding resin and colorant; and an external additive that is externally added to a surface of the toner mother particles, wherein the external additive includes polymethyl methacrylate that is within a range from approximately 0.4 parts by weight to approximately 0.8 parts by weight inclusive per 100 parts by weight of the toner mother particles and that has positive chargeability.
摘要翻译：负电荷显影剂包括：至少包含结合树脂和着色剂的带负电荷的调色剂母粒; 和外部添加剂，其外部添加到调色剂母粒子的表面，其中外部添加剂包括聚对甲基丙烯酸甲酯，其在约每100重量份调色剂约0.4重量份至约0.8重量份的范围内母粒，具有正带电性。

6. 发明申请

US20100124433A1 Developer, developer storing body, developing device and image forming apparatus 审中-公开
标题翻译：显影剂，显影剂储存体，显影装置和图像形成装置
公开(公告)号：US20100124433A1
公开(公告)日：2010-05-20
申请号：US12591035
申请日：2009-11-05
申请人： Yuki Matsuura
发明人： Yuki Matsuura
IPC分类号： G03G21/16 , G03G9/08 , G03G15/08
CPC分类号： G03G9/0819 , G03G9/0804 , G03G9/0821 , G03G9/0827 , G03G9/08708 , G03G9/08755 , G03G9/08766 , G03G9/08793 , G03G9/09725
摘要： A developer includes a toner containing toner mother particles and external additives added to the toner mother particles. The toner mother particles contain at least a resin and a coloring agent. 1.5 to 3.0 weight parts of the external additives are added to 100 weight parts of the toner mother particles. The toner has a mean volume diameter in a range from 6.5 to 8.0 μm, and a surface roughness Rzjis in a range from 75.3 to 236.9 nm as measured using a scanning probe microscope.
摘要翻译：显影剂包括添加到调色剂母粒中的调色剂母体颗粒和外部添加剂的调色剂。调色剂母粒含有至少一种树脂和着色剂。将1.5至3.0重量份的外部添加剂加入到100重量份的调色剂母粒中。调色剂的平均体积直径为6.5-8.0μm，表面粗糙度Rzjis为75.3-236.9nm，使用扫描探针显微镜测量。

7. 发明申请

US20050218407A1 Array substrate, liquid crystal display device and method of manufacturing array substrate 审中-公开
标题翻译：阵列基板，液晶显示装置及阵列基板的制造方法
公开(公告)号：US20050218407A1
公开(公告)日：2005-10-06
申请号：US11141025
申请日：2005-06-01
申请人： Yuki Matsuura , Arichika Ishida
发明人： Yuki Matsuura , Arichika Ishida
IPC分类号： G02F1/1362 , H01L21/77 , H01L21/84 , H01L27/12 , H01L27/13 , H01L29/786
CPC分类号： G02F1/13454 , H01L27/1255 , H01L29/78621
摘要： A gate insulating film is formed on a glass substrate on which a plurality of polysilicon films are formed as islands. A first meal layer formed on the gate insulating film is patterned to form gate electrodes on the gate insulating film facing a polysilicon layer which gives rise to thin film transistors. A second metal layer is formed on the gate insulating film to cover the gate electrodes. Wiring portions are stacked on the gate electrodes of the thin film transistors.
摘要翻译：在其上形成有多个多晶硅膜的玻璃基板上形成栅绝缘膜。形成在栅极绝缘膜上的第一餐层被图案化以在面向多晶硅层的栅极绝缘膜上形成栅电极，从而产生薄膜晶体管。第二金属层形成在栅绝缘膜上以覆盖栅电极。布线部分堆叠在薄膜晶体管的栅电极上。

8. 发明授权

US08431299B2 Developer, image forming unit and image forming apparatus 失效
标题翻译：显影剂，成像单元和图像形成装置
公开(公告)号：US08431299B2
公开(公告)日：2013-04-30
申请号：US12706140
申请日：2010-02-16
申请人： Yuki Matsuura
发明人： Yuki Matsuura
IPC分类号： G03G9/00
CPC分类号： G03G9/0821 , G03G9/08711 , G03G9/08795 , G03G9/08797 , G03G9/09708 , G03G9/09725 , G03G2215/0604
摘要： A developer has a molecular weight distribution of its tetrahydrofuran soluble portion measured by a gel permeation chromatography. In the molecular weight distribution, the main peak is in a range from 2×103 to 3×104 weight-average molecular weight (Mw), the shoulder peak is in a range from 200 to 500 Mw, and a half-value width of the main peak is equal to or less than 50000. A glass-transition temperature Tg of the developer is a range from 55° C. to 80° C.
摘要翻译：显影剂具有通过凝胶渗透色谱测量的其四氢呋喃可溶部分的分子量分布。在分子量分布中，主峰在2×10 3〜3×10 4重均分子量（Mw）的范围内，肩峰在200〜500Mw的范围内，半值宽度主峰等于或小于50000.显影剂的玻璃化转变温度Tg在55℃至80℃的范围内。

9. 发明申请

US20050175912A1 Electrophotographic photosensitive devices and manufacturing methods thereof 审中-公开
标题翻译：电子照相感光装置及其制造方法
公开(公告)号：US20050175912A1
公开(公告)日：2005-08-11
申请号：US11030314
申请日：2005-01-07
申请人： Ikuo Takaki , Yoichi Nakamura , Yuki Matsuura
发明人： Ikuo Takaki , Yoichi Nakamura , Yuki Matsuura
IPC分类号： G03G5/05 , G03G5/02 , G03G5/047 , G03G5/06
CPC分类号： G03G5/0546 , G03G5/0542 , G03G5/0696
摘要： An improved electrophotographic photosensitive device is disclosed. The device comprises a photosensitive layer coupled to a conductive substrate. The photosensitive layer preferably includes a vinyl chloride resin and the vinyl chloride resin preferably comprises an acid esterified vinyl chloride polymer having polymer hydroxy groups, epoxy groups and strong acid radicals as substituent groups, so that the epoxy groups and the hydroxy groups are partially esterified.
摘要翻译：公开了一种改进的电子照相感光装置。该器件包括耦合到导电衬底的感光层。感光层优选包括氯乙烯树脂，并且氯乙烯树脂优选包含具有聚合物羟基的酸酯化的氯乙烯聚合物，环氧基和强酸基作为取代基，使得环氧基和羟基被部分酯化。

10. 发明申请

US20050017318A1 Circuit array substrate and method of manufacturing the same 失效
标题翻译：电路阵列基板及其制造方法
公开(公告)号：US20050017318A1
公开(公告)日：2005-01-27
申请号：US10888755
申请日：2004-07-12
申请人： Arichika Ishida , Masayoshi Fuchi , Yuki Matsuura , Norio Tada
发明人： Arichika Ishida , Masayoshi Fuchi , Yuki Matsuura , Norio Tada
IPC分类号： G02F1/1368 , G02F1/133 , G02F1/136 , G03F7/20 , G09F9/30 , H01L21/336 , H01L27/146 , H01L29/786 , H01L31/00 , H01L31/10 , H01L31/105 , H01L51/50 , H05B33/10 , H05B33/14
CPC分类号： H01L27/3269 , H01L27/14643 , H01L31/1055
摘要： A circuit array substrate is provided with thin-film transistors 4 and 5 and PIN diode 6 formed on insulation substrate 3. Active layer 11 and photo-electric sensor portion 21 are made of poly-silicon films. Impurities are doped into active layer 11 and photo-electric sensor portion 21 in the same process chamber, if necessary, to make their impurity concentrations different from each other. Thin-film transistors 4 and 5 with prescribed characteristics and PIN diode 6 with improved photosensitivity can be simultaneously, easily manufactured on insulation substrate 3 with a lesser number of processes.
摘要翻译：电路阵列基板设置有形成在绝缘基板3上的薄膜晶体管4,5和PIN二极管6.有源层11和光电传感器部分21由多晶硅膜制成。如果需要，将杂质掺杂到相同处理室中的有源层11和光电传感器部分21中，以使它们的杂质浓度彼此不同。具有规定特性的薄膜晶体管4和5以及具有改善光敏性的PIN二极管6可以同时以较少的工艺制造在绝缘基板3上。

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