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    • 3. 发明申请
    • GATE DRIVING CIRCUIT OF DISPLAY PANEL
    • 显示面板的门驱动电路
    • US20110025658A1
    • 2011-02-03
    • US12582716
    • 2009-10-21
    • Yu-Chieh FangLiang-Hua Yeh
    • Yu-Chieh FangLiang-Hua Yeh
    • G06F3/038
    • G09G3/3677G09G2320/0257
    • A gate driving circuit of a display panel including a plurality of shift register sets coupled in series is provided. Every shift register set includes a shift register unit and a transistor coupled therewith. The shift register units receive a gate timing signal and an inverted gate timing signal, and one of a first level shift register unit and a last level shift register unit further receives a threshold driving signal. The shift register units respectively output a plurality of gate driving signals sequentially according to the threshold driving signal, the gate timing signal and the inverted gate timing signal. A gate and a first source/drain of each transistor are coupled to receive a gate controlling signal, and a second source/drain of each transistor is coupled to the corresponding shift register unit to output one of the gate driving signals.
    • 提供了包括串联耦合的多个移位寄存器组的显示面板的栅极驱动电路。 每个移位寄存器组包括移位寄存器单元和与其耦合的晶体管。 移位寄存器单元接收门定时信号和反相门定时信号,并且第一电平移位寄存器单元和最后电平移位寄存器单元中的一个进一步接收阈值驱动信号。 移位寄存器单元根据阈值驱动信号,门定时信号和反相门定时信号分别输出多个栅极驱动信号。 每个晶体管的栅极和第一源极/漏极被耦合以接收栅极控制信号,并且每个晶体管的第二源极/漏极耦合到相应的移位寄存器单元以输出栅极驱动信号之一。
    • 4. 发明授权
    • Gate driving circuit of display panel including shift register sets
    • 显示面板的门驱动电路包括移位寄存器组
    • US08305330B2
    • 2012-11-06
    • US12582716
    • 2009-10-21
    • Yu-Chieh FangLiang-Hua Yeh
    • Yu-Chieh FangLiang-Hua Yeh
    • G09G3/36
    • G09G3/3677G09G2320/0257
    • A gate driving circuit of a display panel including a plurality of shift register sets coupled in series is provided. Every shift register set includes a shift register unit and a transistor coupled therewith. The shift register units receive a gate timing signal and an inverted gate timing signal, and one of a first level shift register unit and a last level shift register unit further receives a threshold driving signal. The shift register units respectively output a plurality of gate driving signals sequentially according to the threshold driving signal, the gate timing signal and the inverted gate timing signal. A gate and a first source/drain of each transistor are coupled to receive a gate controlling signal, and a second source/drain of each transistor is coupled to the corresponding shift register unit to output one of the gate driving signals.
    • 提供了包括串联耦合的多个移位寄存器组的显示面板的栅极驱动电路。 每个移位寄存器组包括移位寄存器单元和与其耦合的晶体管。 移位寄存器单元接收门定时信号和反相门定时信号,并且第一电平移位寄存器单元和最后电平移位寄存器单元中的一个进一步接收阈值驱动信号。 移位寄存器单元根据阈值驱动信号,门定时信号和反相门定时信号分别输出多个栅极驱动信号。 每个晶体管的栅极和第一源极/漏极被耦合以接收栅极控制信号,并且每个晶体管的第二源极/漏极耦合到相应的移位寄存器单元以输出栅极驱动信号之一。
    • 8. 发明申请
    • DISPLAY
    • 显示
    • US20110254818A1
    • 2011-10-20
    • US12794788
    • 2010-06-07
    • Yu-Chieh FangLiang-Hua Yeh
    • Yu-Chieh FangLiang-Hua Yeh
    • G09G5/00
    • G09G3/3677G09G3/3614G09G2300/0426G09G2310/0205G09G2310/0224
    • A display including a control circuit, a first gate driver, a second gate driver, and pixel unit groups is provided. Each pixel unit group includes a first pixel unit, a second pixel unit, a third pixel unit and a fourth pixel unit. The control circuit provides a first start signal and a second start signal to the first gate driver and the second gate driver respectively. In a first frame period, the first start signal is provided, and then after a period, the second start signal is provided to drive the first pixel unit, the second pixel unit, the third pixel unit and the fourth pixel unit sequentially. In a second frame period, the second start signal is provided, and then after a period, the first start signal is provided to drive the second pixel unit, the first pixel unit, the fourth pixel unit and the third pixel unit sequentially.
    • 提供了包括控制电路,第一栅极驱动器,第二栅极驱动器和像素单元组的显示器。 每个像素单元组包括第一像素单元,第二像素单元,第三像素单元和第四像素单元。 控制电路分别向第一栅极驱动器和第二栅极驱动器提供第一启动信号和第二启动信号。 在第一帧周期中,提供第一起始信号,然后在一段时间之后,提供第二起始信号以依次驱动第一像素单元,第二像素单元,第三像素单元和第四像素单元。 在第二帧周期中,提供第二起始信号,然后在一段时间之后,提供第一起始信号以依次驱动第二像素单元,第一像素单元,第四像素单元和第三像素单元。