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2. 发明授权

US5610865A Semiconductor memory device with redundancy structure 失效
标题翻译：具有冗余结构的半导体存储器件
公开(公告)号：US5610865A
公开(公告)日：1997-03-11
申请号：US480785
申请日：1995-06-07
申请人： Choong-Sun Shin , Young-Sik Seok
发明人： Choong-Sun Shin , Young-Sik Seok
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/84
摘要： A semiconductor memory device with redundancy structure having a normal memory cell array having a plurality of normal memory cells arranged in row and column directions and a redundant memory cell array having a plurality of redundant memory cells, includes a redundant column selecting circuit for comparing an externally applied column address signal and a programmed defective column address signal to generate a redundant column selection signal. The redundant column selecting circuit has a programming circuit portion for producing the programmed defective column address signal by programming a defective column address corresponding to a defective column. A decoding circuit is provided for decoding the column address signals and producing a column decoding signal; and a normal column selecting circuit for receiving the column decoding signal and producing a normal column selection signal, and which has a disabling circuit for disabling the normal column selecting circuit and enabling the redundant column selecting circuit when the defective column address is applied. When a redundant column is substituted for a defective column with the present invention, since the normal column selection circuit can be operated independently of output signals of fusing boxes provided in a redundant column selection circuit, mal-operation of column and redundant selection circuits can be prevented and the gate passing time of a signal is shortened so as to achieve a high speed operation of the circuits.
摘要翻译：一种具有冗余结构的半导体存储器件，具有正常存储单元阵列，具有排列成行和列方向的多个正常存储单元，以及具有多个冗余存储单元的冗余存储单元阵列，包括冗余列选择电路，用于比较外部应用列地址信号和编程的缺陷列地址信号以产生冗余列选择信号。冗余列选择电路具有编程电路部分，用于通过对与缺陷列相对应的有缺陷的列地址进行编程来产生编程的缺陷列地址信号。提供解码电路用于对列地址信号进行解码并产生列解码信号; 以及正常列选择电路，用于接收列解码信号并产生正常列选择信号，并且具有用于禁用正常列选择电路的禁止电路，并且当应用有缺陷列地址时使能冗余列选择电路。当利用本发明代替缺陷列的冗余列时，由于可以独立于设置在冗余列选择电路中的定影盒的输出信号来操作正常列选择电路，所以列和冗余选择电路的错误操作可以是并且信号的通过时间被缩短以便实现电路的高速操作。

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