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1. 发明申请

US20100041200A1 Semiconductor transistor device and method for manufacturing the same 审中-公开
标题翻译：半导体晶体管器件及其制造方法
公开(公告)号：US20100041200A1
公开(公告)日：2010-02-18
申请号：US12461428
申请日：2009-08-11
申请人： Young Seong Lee
发明人： Young Seong Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/7834 , H01L29/665 , H01L29/6656 , H01L29/66628
摘要： A semiconductor transistor device and a method for manufacturing the same are provided. The method includes forming a silicon epitaxial layer having a predetermined thickness in source and drain diffusion regions of a silicon semiconductor substrate and forming a source and drain junction by ion implantation and rapid annealing in the silicon semiconductor substrate in which the silicon epitaxial layer is formed. The semiconductor transistor device includes a silicon epitaxial layer formed to have a predetermined thickness in source and drain diffusion regions of a silicon semiconductor substrate. Thus, since a salicide layer is used without increase of leakage current, the transistor device having low power and high performance can be manufactured.
摘要翻译：提供一种半导体晶体管器件及其制造方法。该方法包括在硅半导体衬底的源极和漏极扩散区域中形成具有预定厚度的硅外延层，并在其中形成硅外延层的硅半导体衬底中通过离子注入和快速退火形成源极和漏极结。半导体晶体管器件包括在硅半导体衬底的源极和漏极扩散区域中形成为具有预定厚度的硅外延层。因此，由于在不增加泄漏电流的情况下使用自对准硅化物层，所以可以制造具有低功率和高性能的晶体管器件。

2. 发明申请

US20070161175A1 METHOD FOR FORMING A GATE INSULATING LAYER OF A SEMICONDUCTOR DEVICE 失效
标题翻译：形成半导体器件栅极绝缘层的方法
公开(公告)号：US20070161175A1
公开(公告)日：2007-07-12
申请号：US11616284
申请日：2006-12-26
申请人： Young Seong Lee
发明人： Young Seong Lee
IPC分类号： H01L21/8238
CPC分类号： H01L21/823462
摘要： Embodiments relate to a method for forming a gate insulating layer, which may include forming a device isolation layer being divided into a device active region and a device isolation region, growing a first oxide layer at an entire surface of the semiconductor substrate as a gate insulating layer, performing a first annealing process to form a diffusion barrier layer an interface between the first oxide layer and the device active region, etching and removing a first oxide layer and a diffusion barrier layer of the core power source wiring region by masking the input/output power source wiring region, growing a second oxide layer on the core power source wiring region, and performing a second annealing process to form an NO gate oxide layer on which an N-rich oxide layer at an interface of the core power source wiring region.
摘要翻译：实施例涉及形成栅极绝缘层的方法，其可以包括形成被分为器件有源区和器件隔离区的器件隔离层，在半导体衬底的整个表面上生长第一氧化物层作为栅极绝缘进行第一退火处理，以形成扩散阻挡层，在第一氧化物层和器件有源区之间形成界面，通过掩蔽输入/输出的方式蚀刻并去除芯电源布线区域的第一氧化物层和扩散阻挡层，输出电源布线区域，在芯电源布线区域上生长第二氧化物层，并且进行第二退火处理，以形成在其上的核心电源布线区域的界面处的富N氧化物层的NO栅极氧化物层。

3. 发明授权

US06855616B2 Methods for manufacturing semiconductor devices 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06855616B2
公开(公告)日：2005-02-15
申请号：US10694489
申请日：2003-10-27
申请人： Young Seong Lee
发明人： Young Seong Lee
IPC分类号： H01L21/314 , H01L21/316 , H01L21/762 , H01L21/76
CPC分类号： H01L21/3141 , H01L21/02216 , H01L21/0228 , H01L21/31612 , H01L21/76227
摘要： A method of producing a semiconductor device, wherein after a trench is formed on a field region of a semiconductor substrate, an adsorption reaction of TEOS and a decomposition/recomposition reaction of TEOS using as a catalyst oxygen atoms decomposed from O3 are independently and repeatedly performed. As disclosed, the oxide layer can be buried in the trench with a fine width without generating voids therein, increasing electrical property of the semiconductor device.
摘要翻译：一种制造半导体器件的方法，其中在半导体衬底的场区上形成沟槽之后，独立且重复地执行TEOS的吸附反应和TEOS的分解/重新组成反应，作为从O 3分解的氧原子的催化剂。如所公开的那样，氧化物层可以以细的宽度掩埋在沟槽中，而不会在其中产生空隙，从而增加半导体器件的电性能。

4. 发明授权

US07675128B2 Method for forming a gate insulating layer of a semiconductor device 失效
标题翻译：用于形成半导体器件的栅极绝缘层的方法
公开(公告)号：US07675128B2
公开(公告)日：2010-03-09
申请号：US12352374
申请日：2009-01-12
申请人： Young Seong Lee
发明人： Young Seong Lee
IPC分类号： H01L21/8238
CPC分类号： H01L21/823462
摘要： Embodiments relate to a method for forming a gate insulating layer, which may include forming a device isolation layer being divided into a device active region and a device isolation region, growing a first oxide layer at an entire surface of the semiconductor substrate as a gate insulating layer, performing a first annealing process to form a diffusion barrier layer an interface between the first oxide layer and the device active region, etching and removing a first oxide layer and a diffusion barrier layer of the core power source wiring region by masking the input/output power source wiring region, growing a second oxide layer on the core power source wiring region, and performing a second annealing process to form an NO gate oxide layer on which an N-rich oxide layer at an interface of the core power source wiring region.
摘要翻译：实施例涉及形成栅极绝缘层的方法，其可以包括形成被分为器件有源区和器件隔离区的器件隔离层，在半导体衬底的整个表面上生长第一氧化物层作为栅极绝缘进行第一退火处理，以形成扩散阻挡层，在第一氧化物层和器件有源区之间形成界面，通过掩蔽输入/输出的方式蚀刻并去除芯电源布线区域的第一氧化物层和扩散阻挡层，输出电源布线区域，在芯电源布线区域上生长第二氧化物层，并进行第二退火处理，以形成在其上的核心电源布线区域的界面处的富N氧化物层的NO栅极氧化层。

5. 发明授权

US07589027B2 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07589027B2
公开(公告)日：2009-09-15
申请号：US11616049
申请日：2006-12-26
申请人： Young Seong Lee
发明人： Young Seong Lee
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/823462 , H01L21/3144
摘要： Provided is a method of manufacturing a semiconductor device. A first gate oxide layer is formed on a semiconductor substrate in which a core region and an input/output region are defined. The first gate oxide layer of the core region is selectively removed, and a second gate oxide layer is formed under the first gate oxide layer of the input/output region and on the semiconductor substrate of the core region. Nitrogen annealing is performed to form a nitrogen-rich oxide layer under the second gate oxide layer. An additional thermal process is performed to diffuse nitrogen segregated on an interface between the first gate oxide layer and the second gate oxide layer of the input/output region to a surface of the semiconductor substrate. Impurities generated during the additional thermal process are discharged to the outside.
摘要翻译：提供一种制造半导体器件的方法。在其中限定了核心区域和输入/输出区域的半导体衬底上形成第一栅极氧化物层。选择性地去除芯区域的第一栅极氧化物层，并且在输入/输出区域的第一栅极氧化物层和核心区域的半导体衬底之下形成第二栅极氧化物层。进行氮退火以在第二栅极氧化物层下方形成富氮氧化物层。进行另外的热处理以将分离在输入/输出区域的第一栅极氧化物层和第二栅极氧化物层之间的界面上的氮扩散到半导体衬底的表面。在额外的热处理过程中产生的杂质排放到外部。

6. 发明授权

US07524720B2 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07524720B2
公开(公告)日：2009-04-28
申请号：US11616055
申请日：2006-12-26
申请人： Young Seong Lee
发明人： Young Seong Lee
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823842 , Y10S438/981
摘要： A method of manufacturing a semiconductor device is provided. The method includes the steps of forming a gate oxide layer including an oxide layer containing a large amount of nitrogen on a semiconductor substrate on which an input/output (I/O) region including an NMOS region and a PMOS region are defined, forming a polysilicon on the gate oxide layer, selectively removing the polysilicon on the PMOS region, selectively removing the gate oxide layer on the PMOS region, forming a pure SiO2 layer on the semiconductor substrate of the PMOS region, removing a surface oxide layer on the remaining polysilicon generated when the pure SiO2 layer is formed, and forming a gate electrode polysilicon on the entire surface including the remaining polysilicon.
摘要翻译：提供一种制造半导体器件的方法。该方法包括以下步骤：在其上限定有包括NMOS区和PMOS区的输入/输出（I / O）区域的半导体衬底上形成包含含有大量氮的氧化物层的栅氧化层，形成选择性地去除PMOS区上的多晶硅，选择性地除去PMOS区上的栅极氧化层，在PMOS区的半导体衬底上形成纯SiO 2层，去除剩余多晶硅上的表面氧化物层在形成纯SiO 2层时产生，并且在包括剩余的多晶硅的整个表面上形成栅电极多晶硅。

7. 发明申请

US20070171741A1 METHOD OF CURING ANALOG DEVICE FAIL THROUGH FAST TRANSISTOR 审中-公开
标题翻译：通过快速晶体管固化模拟器件失效的方法
公开(公告)号：US20070171741A1
公开(公告)日：2007-07-26
申请号：US11617129
申请日：2006-12-28
申请人： Young Seong Lee , Kye Lee
发明人： Young Seong Lee , Kye Lee
IPC分类号： G11C29/00
CPC分类号： H01L22/20
摘要： Disclosed is a method of curing a failure of an analog device, wherein the operational range of a transistor is optimized, thereby curing a failure in the analog device and enhancing a yield. In the method, the target of the 1.5V high transistor is modified to a fast condition, thereby eliminating the ring type failure phenomenon caused by Fmax. To this end, the manufacturing margin of a threshold voltage is set as 100 mV, the control specification of GC CD (Critical dimension) is set as ±0.013 μm, and the thickness specification of a gate oxide is set as 23±1 Å.
摘要翻译：公开了一种固化模拟装置的故障的方法，其中晶体管的工作范围被优化，从而固化模拟装置的故障并提高产量。在该方法中，将1.5V高晶体管的目标修改为快速状态，从而消除由F最大值引起的环型故障现象。为此，将阈值电压的制造裕度设定为100mV，GC CD（临界尺寸）的控制规格设定为±0.013μm，栅极氧化物的厚度规格设定为23±1。

8. 发明授权

US07494879B2 Method for forming a gate insulating layer of a semiconductor device 失效
标题翻译：用于形成半导体器件的栅极绝缘层的方法
公开(公告)号：US07494879B2
公开(公告)日：2009-02-24
申请号：US11616284
申请日：2006-12-26
申请人： Young Seong Lee
发明人： Young Seong Lee
IPC分类号： H01L21/8238
CPC分类号： H01L21/823462
摘要： Embodiments relate to a method for forming a gate insulating layer, which may include forming a device isolation layer being divided into a device active region and a device isolation region, growing a first oxide layer at an entire surface of the semiconductor substrate as a gate insulating layer, performing a first annealing process to form a diffusion barrier layer an interface between the first oxide layer and the device active region, etching and removing a first oxide layer and a diffusion barrier layer of the core power source wiring region by masking the input/output power source wiring region, growing a second oxide layer on the core power source wiring region, and performing a second annealing process to form an NO gate oxide layer on which an N-rich oxide layer at an interface of the core power source wiring region.
摘要翻译：实施例涉及形成栅极绝缘层的方法，其可以包括形成被分为器件有源区和器件隔离区的器件隔离层，在半导体衬底的整个表面上生长第一氧化物层作为栅极绝缘进行第一退火处理，以形成扩散阻挡层，在第一氧化物层和器件有源区之间形成界面，通过掩蔽输入/输出的方式来蚀刻和去除芯电源布线区域的第一氧化物层和扩散阻挡层，输出电源布线区域，在芯电源布线区域上生长第二氧化物层，并进行第二退火处理，以形成在其上的核心电源布线区域的界面处的富N氧化物层的NO栅极氧化层。

9. 发明申请

US20090127671A1 METHOD FOR FORMING A GATE INSULATING LAYER OF A SEMICONDUCTOR DEVICE 失效
标题翻译：形成半导体器件栅极绝缘层的方法
公开(公告)号：US20090127671A1
公开(公告)日：2009-05-21
申请号：US12352374
申请日：2009-01-12
申请人： Young Seong Lee
发明人： Young Seong Lee
IPC分类号： H01L29/06
CPC分类号： H01L21/823462
摘要： Embodiments relate to a method for forming a gate insulating layer, which may include forming a device isolation layer being divided into a device active region and a device isolation region, growing a first oxide layer at an entire surface of the semiconductor substrate as a gate insulating layer, performing a first annealing process to form a diffusion barrier layer an interface between the first oxide layer and the device active region, etching and removing a first oxide layer and a diffusion barrier layer of the core power source wiring region by masking the input/output power source wiring region, growing a second oxide layer on the core power source wiring region, and performing a second annealing process to form an NO gate oxide layer on which an N-rich oxide layer at an interface of the core power source wiring region.
摘要翻译：实施例涉及形成栅极绝缘层的方法，其可以包括形成被分为器件有源区和器件隔离区的器件隔离层，在半导体衬底的整个表面上生长第一氧化物层作为栅极绝缘进行第一退火处理，以形成扩散阻挡层，在第一氧化物层和器件有源区之间形成界面，通过掩蔽输入/输出的方式蚀刻并去除芯电源布线区域的第一氧化物层和扩散阻挡层，输出电源布线区域，在芯电源布线区域上生长第二氧化物层，并进行第二退火处理，以形成在其上的核心电源布线区域的界面处的富N氧化物层的NO栅极氧化层。

10. 发明申请

US20070161212A1 METHOD FOR MANUFACTURING MOSFET ON SEMICONDUCTOR DEVICE 审中-公开
标题翻译：在半导体器件上制造MOSFET的方法
公开(公告)号：US20070161212A1
公开(公告)日：2007-07-12
申请号：US11616274
申请日：2006-12-26
申请人： Young Seong Lee
发明人： Young Seong Lee
IPC分类号： H01L21/326 , H01L21/479
CPC分类号： H01L21/76802 , H01L21/76814 , H01L21/76883 , H01L23/5256 , H01L24/05 , H01L29/6659 , H01L29/7833 , H01L2224/05556 , H01L2924/1306 , H01L2924/13091 , H01L2924/00
摘要： A method for manufacturing a semiconductor device having a fuse area and a pad area. An inter-layer dielectric layer is deposited over a semiconductor substrate having a metal interconnection. A protection layer is deposited over the inter-layer dielectric layer. A photoresist mask is used to define areas to be etched in the fuse area and a pad area. The protection layer and the inter-layer dielectric layer are etched in the pad area and the fuse area, thereby exposing the metal interconnection in the pad area, and removing the dielectric material to a predetermined depth in a fuse area, using an etching gas including a first component. The first etching process is stopped. A second etching process is performed for selectively etching a surface of the metal interconnection using an etching gas including a second component.
摘要翻译：一种制造具有熔丝区域和焊盘区域的半导体器件的方法。在具有金属互连的半导体衬底上沉积层间电介质层。保护层沉积在层间电介质层上。光致抗蚀剂掩模用于限定保险丝区域中要蚀刻的区域和焊盘区域。在焊盘区域和保险丝区域中蚀刻保护层和层间电介质层，由此暴露焊盘区域中的金属互连，并且使用包括以下的蚀刻气体将介电材料移除到熔丝区域中的预定深度第一个组件。第一蚀刻工艺停止。执行第二蚀刻工艺以使用包括第二部件的蚀刻气体来选择性地蚀刻金属互连件的表面。

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