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1. 发明授权

US07649223B2 Semiconductor device having superjunction structure and method for manufacturing the same 有权
标题翻译：具有超结构结构的半导体装置及其制造方法
公开(公告)号：US07649223B2
公开(公告)日：2010-01-19
申请号：US11819677
申请日：2007-06-28
申请人： Yoshiya Kawashima
发明人： Yoshiya Kawashima
IPC分类号： H01L29/732 , H01L29/772
CPC分类号： H01L29/7811 , H01L29/0623 , H01L29/0634 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/41741 , H01L29/4238 , H01L29/66734 , H01L29/7813
摘要： An n-type drift region includes an active element region and a peripheral region. A p-type base region is formed at least in the active element region. A trench-type gate electrode is formed in each of the active element region and the peripheral region. An n-type source region formed in the base region. A plurality of p-type column regions is selectively formed separately from one another in each of the active element region and the peripheral region. In a peripheral region, a p-type guard region is formed below the gate electrode. In the active element region, the p-type guard region is not formed below the gate electrode. As a result, it is possible to hold the breakdown voltage in the peripheral region at a higher level than in the active element region while maintaining the low ON resistance due to a superjunction structure and to raise the breakdown voltage performance of the semiconductor device.
摘要翻译： n型漂移区域包括有源元件区域和周边区域。至少在有源元件区域中形成p型基极区域。沟槽型栅电极形成在有源元件区域和周边区域的每一个中。在该基区形成的n型源区。多个p型列区域在有源元件区域和周边区域中的每一个中彼此分开地选择性地形成。在外围区域中，在栅电极下形成p型保护区。在有源元件区域中，p型保护区域不形成在栅电极下方。结果，可以将周边区域中的击穿电压保持在比有源元件区域更高的电平，同时保持由于超结构结构引起的低导通电阻并且提高半导体器件的击穿电压性能。

2. 发明申请

US20080001217A1 Semiconductor device having superjunction structure and method for manufacturing the same 有权
标题翻译：具有超结构结构的半导体装置及其制造方法
公开(公告)号：US20080001217A1
公开(公告)日：2008-01-03
申请号：US11819677
申请日：2007-06-28
申请人： Yoshiya Kawashima
发明人： Yoshiya Kawashima
IPC分类号： H01L21/26 , H01L21/336
CPC分类号： H01L29/7811 , H01L29/0623 , H01L29/0634 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/41741 , H01L29/4238 , H01L29/66734 , H01L29/7813
摘要： An n-type drift region includes an active element region and a peripheral region. A p-type base region is formed at least in the active element region. A trench-type gate electrode is formed in each of the active element region and the peripheral region. An n-type source region formed in the base region. A plurality of p-type column regions is selectively formed separately from one another in each of the active element region and the peripheral region. In a peripheral region, a p-type guard region is formed below the gate electrode. In the active element region, the p-type guard region is not formed below the gate electrode. As a result, it is possible to hold the breakdown voltage in the peripheral region at a higher level than in the active element region while maintaining the low ON resistance due to a superjunction structure and to raise the breakdown voltage performance of the semiconductor device.
摘要翻译： n型漂移区域包括有源元件区域和周边区域。至少在有源元件区域中形成p型基极区域。沟槽型栅电极形成在有源元件区域和周边区域的每一个中。在该基区形成的n型源区。多个p型列区域在有源元件区域和周边区域中的每一个中彼此分开地选择性地形成。在外围区域中，在栅电极下形成p型保护区。在有源元件区域中，p型保护区域不形成在栅电极下方。结果，可以将周边区域中的击穿电压保持在比有源元件区域更高的电平，同时保持由于超结构结构引起的低导通电阻并且提高半导体器件的击穿电压性能。

3. 发明申请

US20110266618A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110266618A1
公开(公告)日：2011-11-03
申请号：US13180060
申请日：2011-07-11
申请人： Yoshiya KAWASHIMA
发明人： Yoshiya KAWASHIMA
IPC分类号： H01L27/088
CPC分类号： H01L21/823437 , H01L21/823487 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/7813
摘要： A semiconductor device of the present invention has a first-conductivity-type substrate having second-conductivity-type base regions exposed to a first surface thereof; trench gates provided to a first surface of the substrate; first-conductivity-type source regions formed shallower than the base regions; a plurality of second-conductivity-type column regions located between two adjacent trench gates in a plan view, while being spaced from each other in a second direction normal to the first direction; the center of each column region and the center of each base contact region fall on the center line between two trench gates; and has no column region formed below the trench gates.
摘要翻译：本发明的半导体器件具有第一导电型基板，其具有暴露于其第一表面的第二导电型基极区域; 提供到基板的第一表面的沟槽栅; 形成比基部区域浅的第一导电型源极区域; 多个第二导电型列区域，其在平面图中位于两个相邻的沟槽栅极之间，同时在垂直于第一方向的第二方向上彼此间隔开; 每个列区域的中心和每个基极接触区域的中心落在两个沟槽栅极之间的中心线上; 并且在沟槽栅极下方没有形成列区域。

4. 发明授权

US08536647B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08536647B2
公开(公告)日：2013-09-17
申请号：US13180060
申请日：2011-07-11
申请人： Yoshiya Kawashima
发明人： Yoshiya Kawashima
IPC分类号： H01L29/78 , H01L21/8234 , H01L29/06 , H01L29/10
CPC分类号： H01L21/823437 , H01L21/823487 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/7813
摘要： A semiconductor device of the present invention has a first-conductivity-type substrate having second-conductivity-type base regions exposed to a first surface thereof; trench gates provided to a first surface of the substrate; first-conductivity-type source regions formed shallower than the base regions; a plurality of second-conductivity-type column regions located between two adjacent trench gates in a plan view, while being spaced from each other in a second direction normal to the first direction; the center of each column region and the center of each base contact region fall on the center line between two trench gates; and has no column region formed below the trench gates.
摘要翻译：本发明的半导体器件具有第一导电型基板，其具有暴露于其第一表面的第二导电型基极区域; 提供到基板的第一表面的沟槽栅; 形成比基部区域浅的第一导电型源极区域; 多个第二导电型列区域，其在平面图中位于两个相邻的沟槽栅极之间，同时在垂直于第一方向的第二方向上彼此间隔开; 每个列区域的中心和每个基极接触区域的中心落在两个沟槽栅极之间的中心线上; 并且在沟槽栅极下方没有形成列区域。

5. 发明授权

US08008717B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08008717B2
公开(公告)日：2011-08-30
申请号：US12498774
申请日：2009-07-07
申请人： Yoshiya Kawashima
发明人： Yoshiya Kawashima
IPC分类号： H01L29/78
CPC分类号： H01L21/823437 , H01L21/823487 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/7813
摘要： A semiconductor device of the present invention has a first-conductivity-type substrate having second-conductivity-type base regions exposed to a first surface thereof; trench gates provided to a first surface of the substrate; first-conductivity-type source regions formed shallower than the base regions; a plurality of second-conductivity-type column regions located between two adjacent trench gates in a plan view, while being spaced from each other in a second direction normal to the first direction; the center of each column region and the center of each base contact region fall on the center line between two trench gates; and has no column region formed below the trench gates.
摘要翻译：本发明的半导体器件具有第一导电型基板，其具有暴露于其第一表面的第二导电型基极区域; 提供到基板的第一表面的沟槽栅; 形成比基部区域浅的第一导电型源极区域; 多个第二导电型列区域，其在平面图中位于两个相邻的沟槽栅极之间，同时在垂直于第一方向的第二方向上彼此间隔开; 每个列区域的中心和每个基极接触区域的中心落在两个沟槽栅极之间的中心线上; 并且在沟槽栅极下方没有形成列区域。

6. 发明授权

US08643103B2 Semiconductor device including gate contact region and protruding gate electrode 有权
标题翻译：半导体器件包括栅极接触区域和突出栅电极
公开(公告)号：US08643103B2
公开(公告)日：2014-02-04
申请号：US13244445
申请日：2011-09-24
申请人： Yoshiya Kawashima
发明人： Yoshiya Kawashima
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0696 , H01L29/0869 , H01L29/1095 , H01L29/41766 , H01L29/4236 , H01L29/42372 , H01L29/4238 , H01L29/66727 , H01L29/66734 , H01L29/7397 , H01L29/7811
摘要： A semiconductor device for preventing an outer well from being separated by a trench gate electrode from the well of a cell region while suppressing increase in the gate resistance in which buried gate electrodes extending in a direction overlapping a gate contact region extend only before a gate electrode so as not to overlap the gate electrode, the source contact situated between each of the buried gate electrodes is shorter than the buried gate electrode in the vertical direction, the ends of the buried gate electrodes on the side of the gate electrode are connected with each other by a buried connecting electrode disposed before the gate electrode, the buried connecting electrode extends in a direction parallel with the longer side of the semiconductor device, and is not connected to the buried gate electrode on the side of the contact situated adjacent to the contact-side buried gate electrode.
摘要翻译：一种半导体器件，用于防止外部阱被单元区域的阱分离，同时抑制栅极电阻的增加，其中在与栅极接触区域重叠的方向上延伸的掩埋栅电极仅在栅电极之前延伸为了不与栅电极重叠，位于每个掩埋栅电极之间的源极触点在垂直方向上比掩埋栅电极短，栅电极一侧的掩埋栅电极的端部与每个另外，通过设置在栅电极之前的埋置连接电极，埋入连接电极在与半导体器件的长边平行的方向上延伸，并且不与位于邻近触点的触点侧的掩埋栅极连接侧埋电极。

7. 发明授权

US07829417B2 Semiconductor apparatus and method of manufacturing semiconductor apparatus 失效
标题翻译：半导体装置及半导体装置的制造方法
公开(公告)号：US07829417B2
公开(公告)日：2010-11-09
申请号：US12128865
申请日：2008-05-29
申请人： Hitoshi Ninomiya , Yoshinao Miura , Yoshiya Kawashima
发明人： Hitoshi Ninomiya , Yoshinao Miura , Yoshiya Kawashima
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/266 , H01L29/0634 , H01L29/1095 , H01L29/66734
摘要： A semiconductor apparatus with a superjunction structure includes a gate electrode which fills a trench that is formed in an epitaxial layer, and a column region which is surrounded by the gate electrode in a plane view. A photomask for forming the column region is elaborated. The photomask has a compensation pattern that compensates a deformation of a photo resist pattern caused by photo interference and a deformation of the ion implantation region diffused by heat treatment. Therefore extending direction of the gate electrode and the outer edge of the column region are substantially parallel.
摘要翻译：具有超结构结构的半导体装置包括填充形成在外延层中的沟槽的栅极电极和在平面图中被栅电极包围的列区域。阐述了用于形成柱区域的光掩模。光掩模具有补偿图案，其补偿由光干涉引起的光致抗蚀剂图案的变形和通过热处理扩散的离子注入区域的变形。因此，栅电极和列区域的外边缘的延伸方向基本上平行。

8. 发明申请

US20080299726A1 SEMICONDUCTOR APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS 失效
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20080299726A1
公开(公告)日：2008-12-04
申请号：US12128865
申请日：2008-05-29
申请人： Hitoshi NINOMIYA , Yoshinao MIURA , Yoshiya KAWASHIMA
发明人： Hitoshi NINOMIYA , Yoshinao MIURA , Yoshiya KAWASHIMA
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/266 , H01L29/0634 , H01L29/1095 , H01L29/66734
摘要： A semiconductor apparatus with a superjunction structure includes a gate electrode which fills a trench that is formed in an epitaxial layer, and a column region which is surrounded by the gate electrode in a plane view. A photomask for forming the column region is elaborated. The photomask has a compensation pattern that compensates a deformation of a photo resist pattern caused by photo interference and a deformation of the ion implantation region diffused by heat treatment. Therefore extending direction of the gate electrode and the outer edge of the column region are substantially parallel.
摘要翻译：具有超结构结构的半导体装置包括填充形成在外延层中的沟槽的栅极电极和在平面图中被栅电极包围的列区域。阐述了用于形成柱区域的光掩模。光掩模具有补偿图案，其补偿由光干涉引起的光致抗蚀剂图案的变形和通过热处理扩散的离子注入区域的变形。因此，栅电极和列区域的外边缘的延伸方向基本上平行。

9. 发明申请

US20080197381A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080197381A1
公开(公告)日：2008-08-21
申请号：US12029478
申请日：2008-02-12
申请人： Yoshiya Kawashima , Yoshinao Miura , Hitoshi Ninomiya
发明人： Yoshiya Kawashima , Yoshinao Miura , Hitoshi Ninomiya
IPC分类号： H01L29/04 , H01L21/336
CPC分类号： H01L29/7397 , H01L29/66348
摘要： A semiconductor device is provided with a vertical MOSFET including an N-type drift region that has a {110} crystal plane serving as the main surface thereof, a trench gate structure formed in a trench that has a {100} crystal plane serving as a sidewall surface thereof, and plural P-type column region structures provided in the N-type drift region 3, making up the super-junction structure. The P-type column region structures are disposed so as to be separated from each other in a plan view, and each of the plurality of column structures includes a plurality of column regions of the second conductivity type separated from each other in a cross-sectional view. By applying ion implantation of a P-type dopant to the main surface from a direction vertical to the main surface, the P-type column regions are formed down to sufficiently deeper positions in the drift region due to channeling. By so doing, it is possible to obtain a semiconductor device with an enhanced breakdown voltage. Further, since it is possible that a crystal plane of a channel is the {100} crystal plane, enabling a maximum electron mobility to be obtained, it is possible to increase on-current, so that on-resistance can be reduced.
摘要翻译：半导体器件设置有包括具有{110}晶面用作其主表面的N型漂移区的垂直MOSFET，在具有{100}晶面的沟槽中形成的沟槽栅结构，作为以及设置在N型漂移区域3中的多个P型列区域结构，构成超结结构。 P型列区域结构被布置成在平面图中彼此分离，并且多个列结构中的每一个都包括在横截面中彼此分离的多个第二导电类型的列区域视图。通过从垂直于主表面的方向向主表面施加P型掺杂剂的离子注入，P型列区域由于引导而形成在漂移区域中的足够深的位置。通过这样做，可以获得具有增强的击穿电压的半导体器件。此外，由于通道的晶面可以是{100}晶面，因此能够获得最大的电子迁移率，可以增加导通电流，从而可以降低导通电阻。

10. 发明申请

US20120098060A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120098060A1
公开(公告)日：2012-04-26
申请号：US13244445
申请日：2011-09-24
申请人： Yoshiya Kawashima
发明人： Yoshiya Kawashima
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0696 , H01L29/0869 , H01L29/1095 , H01L29/41766 , H01L29/4236 , H01L29/42372 , H01L29/4238 , H01L29/66727 , H01L29/66734 , H01L29/7397 , H01L29/7811
摘要： A semiconductor device for preventing an outer well from being separated by a trench gate electrode from the well of a cell region while suppressing increase in the gate resistance in which buried gate electrodes extending in a direction overlapping a gate contact region extend only before a gate electrode so as not to overlap the gate electrode, the source contact situated between each of the buried gate electrodes is shorter than the buried gate electrode in the vertical direction, the ends of the buried gate electrodes on the side of the gate electrode are connected with each other by a buried connecting electrode disposed before the gate electrode, the buried connecting electrode extends in a direction parallel with the longer side of the semiconductor device, and is not connected to the buried gate electrode on the side of the contact situated adjacent to the contact-side buried gate electrode.
摘要翻译：一种半导体器件，用于防止外部阱被单元区域的阱分离，同时抑制栅极电阻的增加，其中在与栅极接触区域重叠的方向上延伸的掩埋栅电极仅在栅电极之前延伸为了不与栅电极重叠，位于每个掩埋栅电极之间的源极触点在垂直方向上比掩埋栅电极短，栅电极一侧的掩埋栅电极的端部与每个另外，通过设置在栅电极之前的埋置连接电极，埋入连接电极在与半导体器件的长边平行的方向上延伸，并且不与位于邻近触点的触点侧的掩埋栅极连接侧埋电极。

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