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1. 发明授权

US08008667B2 Semiconductor device including a transparent semiconductor layer for viewing an underlying transistor in a semiconductor substrate 有权
标题翻译：半导体器件包括用于观察半导体衬底中的底层晶体管的透明半导体层
公开(公告)号：US08008667B2
公开(公告)日：2011-08-30
申请号：US11955672
申请日：2007-12-13
申请人： Hidetoshi Koyama , Yoshitaka Kamo
发明人： Hidetoshi Koyama , Yoshitaka Kamo
IPC分类号： H01L29/04 , H01L29/15 , H01L31/036
CPC分类号： H01L27/0688 , H01L21/0237 , H01L21/02378 , H01L21/02458 , H01L21/0254
摘要： A semiconductor device includes a first semiconductor layer and a first semiconductor element located in the first semiconductor layer. The semiconductor device also includes a second semiconductor layer of a transparent semiconductor material. The second semiconductor layer is disposed on the first semiconductor layer covering the first semiconductor element. The semiconductor device also includes a second semiconductor element located in the second semiconductor layer. The semiconductor device also includes a wire extending within the second semiconductor layer and electrically connecting the first and second semiconductor elements.
摘要翻译：半导体器件包括位于第一半导体层中的第一半导体层和第一半导体元件。半导体器件还包括透明半导体材料的第二半导体层。第二半导体层设置在覆盖第一半导体元件的第一半导体层上。半导体器件还包括位于第二半导体层中的第二半导体元件。半导体器件还包括在第二半导体层内延伸的电线，并电连接第一和第二半导体元件。

2. 发明授权

US6151695A Test method of chips in a semiconductor wafer employing a test algorithm 失效
标题翻译：使用测试算法的半导体晶片中芯片的测试方法
公开(公告)号：US6151695A
公开(公告)日：2000-11-21
申请号：US126736
申请日：1998-07-31
申请人： Yoshitaka Kamo , Hiroaki Tosa , Tatsushi Higashi , Akihiro Kuroda
发明人： Yoshitaka Kamo , Hiroaki Tosa , Tatsushi Higashi , Akihiro Kuroda
IPC分类号： H01L21/66 , G01R31/28 , G11C29/44
CPC分类号： G01R31/2834
摘要： Sample chips are tested after determining the chip layout on a semiconductor wafer so that one or plural ones of untested chips are surrounded by plural ones of the sample chips that adjoin the untested samples. A good/defective judgment on the untested chips is performed by using predicted good/defective judgment results that are statistically predicted based on results of the sample test and stored statistical data of a defect generation profile including address information that indicates defective chip locations. As a result, the good/defective judgment can be performed with high accuracy even in a case where defective chips are localized in a particular region on the wafer in a concentrated manner.
摘要翻译：在确定半导体晶片上的芯片布局之后测试样品芯片，使得一个或多个未测试芯片被与未测试样品相邻的多个样品芯片包围。通过使用基于样本测试的结果进行统计预测的预测好/缺陷判断结果和包含指示有缺陷的芯片位置的地址信息的缺陷生成曲线的存储的统计数据来执行未测试芯片的良好/有缺陷的判断。结果，即使在集中方式将缺陷芯片定位在晶片上的特定区域的情况下，也可以高精度地执行良好/缺陷判断。

3. 发明授权

US08809989B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08809989B2
公开(公告)日：2014-08-19
申请号：US13845208
申请日：2013-03-18
申请人： Yoshitaka Kamo
发明人： Yoshitaka Kamo
IPC分类号： H01L27/088 , H01L27/06 , H01L27/02 , H01L29/417
CPC分类号： H01L27/088 , H01L27/0207 , H01L27/0605 , H01L29/41758 , H01L29/4238
摘要： A semiconductor device includes: a semiconductor substrate having a hexagonal crystalline structure with a c-axis and c-planes; and transistors on a c plane of the semiconductor substrate. Source electrodes of the transistors are connected to each other. Drain electrodes of the transistors are connected to each other. Gate electrodes of the transistors are connected to each other. The gate electrodes of the transistors extend along directions that form angles with each other that are 60 degrees or 120 degrees, in a plan view seen from a direction perpendicular to the c plane of the semiconductor substrate.
摘要翻译：半导体器件包括：具有c轴和c面的六方晶结构的半导体衬底; 以及半导体衬底的c面上的晶体管。晶体管的源极彼此连接。晶体管的漏极彼此连接。晶体管的栅电极彼此连接。在从垂直于半导体衬底的c面的方向看的平面图中，晶体管的栅电极沿着彼此形成角度为60度或120度的方向延伸。

4. 发明授权

US08778748B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08778748B2
公开(公告)日：2014-07-15
申请号：US13355991
申请日：2012-01-23
申请人： Yoshitaka Kamo
发明人： Yoshitaka Kamo
IPC分类号： H01L21/338 , H01L23/544 , H01L21/04 , H01L29/66
CPC分类号： H01L23/544 , H01L21/0272 , H01L21/0475 , H01L29/0657 , H01L29/42316 , H01L29/66462 , H01L29/66848 , H01L29/778 , H01L2223/54426 , H01L2924/0002 , H01L2924/00
摘要： A method for manufacturing a semiconductor device includes forming a source electrode and a drain electrode on a front face of a semiconductor substrate which is transparent to visible light, forming a front-side gate electrode between the source electrode and the drain electrode on the front face of the semiconductor substrate; forming an aligning mark on a region of the front face of the semiconductor substrate other than a region between the source electrode and the drain electrode, aligning the semiconductor substrate based on the aligning mark that is seen through the semiconductor substrate, and forming a back-side gate electrode on a back face of the semiconductor substrate in a location opposite the front-side gate electrode.
摘要翻译：一种半导体器件的制造方法，包括在对可见光透明的半导体衬底的正面上形成源电极和漏电极，在前表面的源电极和漏电极之间形成前侧栅电极的半导体衬底; 在所述源电极和所述漏极之间的区域之外的所述半导体衬底的正面的区域上形成对准标记，基于通过所述半导体衬底观察的对准标记对准所述半导体衬底，在与前侧栅电极相对的位置的半导体衬底的背面上的侧栅电极。

5. 发明授权

US07304329B2 Field effect transistor 有权
标题翻译：场效应晶体管
公开(公告)号：US07304329B2
公开(公告)日：2007-12-04
申请号：US10985057
申请日：2004-11-10
申请人： Yoshitaka Kamo , Tetsuo Kunii
发明人： Yoshitaka Kamo , Tetsuo Kunii
IPC分类号： H01L31/072 , H01L31/109 , H01L31/0328 , H01L31/0336
CPC分类号： H01L29/66871 , H01L29/41725 , H01L29/812
摘要： A field effect transistor includes a semiconductor substrate having an active region, a source region, and a drain region at an upper portion of the substrate. The active region is located between the source and drain regions. A gate electrode is located on the active region. A source electrode is located on the source region and forms an ohmic contact with the source region. A drain electrode has a base part on and in ohmic contact with the drain region and an extended part having edge close to the gate electrode and over a boundary between the active region and the drain region. An insulating film is located between the boundary and the extended part and has a thickness that increases along a direction from the drain electrode toward the gate electrode in a step-by-step or continuous manner.
摘要翻译：场效应晶体管包括在衬底的上部具有有源区，源极区和漏极区的半导体衬底。有源区位于源区和漏区之间。栅电极位于有源区上。源电极位于源极区上并与源极区形成欧姆接触。漏极电极具有与漏极区域基极和欧姆接触的基极部分，以及具有靠近栅极电极并且在有源区域和漏极区域之间的边界上的边缘的延伸部分。绝缘膜位于边界和延伸部分之间，并且具有沿着从漏电极朝向栅电极的方向逐步或连续地增加的厚度。

6. 发明授权

US06589063B2 Electric contact device for establishing an improved contact with contactors of other device 失效
公开(公告)号：US06589063B2
公开(公告)日：2003-07-08
申请号：US09793701
申请日：2001-02-27
申请人： Yoshitaka Kamo , Hiroaki Tosa , Tatsushi Higashi
发明人： Yoshitaka Kamo , Hiroaki Tosa , Tatsushi Higashi
IPC分类号： H01R1122
CPC分类号： G01R1/0466 , H01L2924/0002 , H01L2924/00
摘要： There are provided an electric contact device for establishing reliable contact with ball contactors or strip contactors of a semiconductor device over contact areas of great area; a semiconductor device test socket using the electric contact device; a semiconductor module using the electric contact device; and a semiconductor device test method. A contact lead having a ring-shape or helical section is provided between a support pole and a movable pole. The movable pole is moved, to thereby bring the contact lead into an expanded state in which the diameter of the ring-shape or helical section becomes larger. A contactor is inserted into the ring-shape or helical section. The contact lead is then brought into a contacted state such that the diameter of the ring-shape or helical section becomes smaller, wherewith the contact lead is wrapped around the periphery of the contactor.

7. 发明授权

US07851831B2 Transistor 有权
标题翻译：晶体管
公开(公告)号：US07851831B2
公开(公告)日：2010-12-14
申请号：US11859846
申请日：2007-09-24
申请人： Hidetoshi Koyama , Yoshitaka Kamo , Toshihiko Shiga
发明人： Hidetoshi Koyama , Yoshitaka Kamo , Toshihiko Shiga
IPC分类号： H01L29/66 , H01L29/00
CPC分类号： H01L29/475 , H01L29/2003 , H01L29/812
摘要： A transistor includes a nitride semiconductor layer and a gate electrode layer. The gate electrode layer includes a tantalum nitride layer on the nitride semiconductor layer. The tantalum nitride layer forms a Schottky junction with the nitride semiconductor layer. The transistor also includes an insulating film on the nitride semiconductor layer. The insulating film surrounds the gate electrode layer. A first portion of the gate electrode layer, in contact with the nitride semiconductor layer, has a higher nitrogen mole fraction than a second portion of the gate electrode layer.
摘要翻译：晶体管包括氮化物半导体层和栅电极层。栅电极层包括在氮化物半导体层上的氮化钽层。氮化钽层与氮化物半导体层形成肖特基结。晶体管还包括在氮化物半导体层上的绝缘膜。绝缘膜围绕栅电极层。与氮化物半导体层接触的栅电极层的第一部分具有比栅电极层的第二部分高的氮摩尔分数。

8. 发明申请

US20090014728A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090014728A1
公开(公告)日：2009-01-15
申请号：US11955672
申请日：2007-12-13
申请人： Hidetoshi Koyama , Yoshitaka Kamo
发明人： Hidetoshi Koyama , Yoshitaka Kamo
IPC分类号： H01L29/12
CPC分类号： H01L27/0688 , H01L21/0237 , H01L21/02378 , H01L21/02458 , H01L21/0254
摘要： A semiconductor device includes a first semiconductor layer and a first semiconductor element located in the first semiconductor layer. The semiconductor device also includes a second semiconductor layer of a transparent semiconductor material. The second semiconductor layer is disposed on the first semiconductor layer covering the first semiconductor element. The semiconductor device also includes a second semiconductor element located in the second semiconductor layer. The semiconductor device also includes a wire extending within the second semiconductor layer and electrically connecting the first and second semiconductor elements.
摘要翻译：半导体器件包括位于第一半导体层中的第一半导体层和第一半导体元件。半导体器件还包括透明半导体材料的第二半导体层。第二半导体层设置在覆盖第一半导体元件的第一半导体层上。半导体器件还包括位于第二半导体层中的第二半导体元件。半导体器件还包括在第二半导体层内延伸的电线，并电连接第一和第二半导体元件。

9. 发明申请

US20080246060A1 TRANSISTOR 有权
标题翻译：晶体管
公开(公告)号：US20080246060A1
公开(公告)日：2008-10-09
申请号：US11859846
申请日：2007-09-24
申请人： Hidetoshi Koyama , Yoshitaka Kamo , Toshihiko Shiga
发明人： Hidetoshi Koyama , Yoshitaka Kamo , Toshihiko Shiga
IPC分类号： H01L29/812
CPC分类号： H01L29/475 , H01L29/2003 , H01L29/812
摘要： A transistor includes a nitride semiconductor layer and a gate electrode layer. The gate electrode layer includes a tantalum nitride layer being formed on the nitride semiconductor layer. The tantalum nitride layer forms a Schottky junction with the nitride semiconductor layer. The transistor also includes an insulating film formed on the nitride semiconductor layer. The insulating film surrounds the gate electrode layer. The portion of the gate electrode layer in contact with the nitride semiconductor layer has a higher nitrogen mole fraction than the other portion of the gate electrode layer.
摘要翻译：晶体管包括氮化物半导体层和栅电极层。栅电极层包括在氮化物半导体层上形成的氮化钽层。氮化钽层与氮化物半导体层形成肖特基结。晶体管还包括形成在氮化物半导体层上的绝缘膜。绝缘膜围绕栅电极层。与氮化物半导体层接触的栅电极层的部分具有比栅电极层的其他部分高的氮摩尔分数。

10. 发明申请

US20050263788A1 Heterojunction field effect semiconductor device 审中-公开
标题翻译：异质结场效应半导体器件
公开(公告)号：US20050263788A1
公开(公告)日：2005-12-01
申请号：US11091474
申请日：2005-03-29
申请人： Tetsuo Kunii , Yoshitsugu Yamamoto , Yoshitaka Kamo
发明人： Tetsuo Kunii , Yoshitsugu Yamamoto , Yoshitaka Kamo
IPC分类号： H01L21/28 , H01L21/338 , H01L29/417 , H01L29/778 , H01L29/80 , H01L29/812 , H01L31/072
CPC分类号： H01L29/802
摘要： A heterojunction field effect transistor comprises a semi-insulating GaAs substrate, an n-InGaAs channel layer on the substrate, and a barrier layer on the n-InGaAs channel layer. The barrier layer is composed of a substantially fully depleted p-AlGaAs layer between two i-AlGaAs layers. A gate electrode is in Schottky contact with the barrier layer. Since the p-AlGaAs layer raises the barrier height in the barrier layer higher than the Schottky barrier, forward gate current is suppressed. In addition, the breakdown voltage is improved since a longer depletion region extends toward the drain side when a reverse bias is applied between the gate and the drain.
摘要翻译：异质结场效应晶体管包括半绝缘GaAs衬底，衬底上的n-InGaAs沟道层和n-InGaAs沟道层上的势垒层。阻挡层由两个i-AlGaAs层之间的基本上完全耗尽的p-AlGaAs层组成。栅电极与阻挡层肖特基接触。由于p-AlGaAs层在阻挡层中提高了高于肖特基势垒的势垒高度，所以正向栅极电流被抑制。此外，当在栅极和漏极之间施加反向偏压时，由于较长的耗尽区域朝着漏极侧延伸，所以击穿电压得到改善。

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