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1. 发明授权

US5745670A Fault tolerant power supply system 失效
标题翻译：容错电源系统
公开(公告)号：US5745670A
公开(公告)日：1998-04-28
申请号：US661368
申请日：1996-06-11
申请人： Yoseph L. Linde
发明人： Yoseph L. Linde
IPC分类号： H02J1/14 , H02J9/06 , G06F11/00 , H03M13/00
CPC分类号： H02J1/14 , H02J9/061 , Y10T307/615 , Y10T307/62
摘要： A fault tolerant power supply system includes a plurality of devices coupled to a common power distribution bus. The devices are arranged and connected in a hierarchical order. The system provides that the devices of higher rank or position in the hierarchy to obtain priority in drawing power from the bus. Each device is coupled to the next adjacent device via a control status line that indicates whether there has been a failure of the power supply of any device higher up in the hierarchy. In the event that the local power supply of a device fails, it can be selectively connected to the power distribution bus to draw power, only if the control status line indicates that there have no failures in the devices having a higher hierarchical rank. Once connected to power distribution bus, if a higher ranking device should experience a power supply failure, the device will be disconnected from the power distribution bus and the higher ranking device connected to the power distribution bus.
摘要翻译：容错电源系统包括耦合到公共配电总线的多个装置。这些设备以分级顺序排列和连接。该系统提供了层次结构中较高等级或位置的设备，从总线获取优先权。每个设备经由控制状态线耦合到下一相邻设备，该控制状态线指示层次结构中是否存在任何设备的电源故障。在设备的本地电源发生故障的情况下，仅当控制状态线指示在具有较高等级等级的设备中没有故障时，才可以选择性地将其连接到配电总线来进行供电。一旦连接到配电总线，如果较高级别的设备应该遇到电源故障，则设备将与配电总线和连接到配电总线的较高排名设备断开连接。

2. 发明授权

US5790057A Method of and system for the efficient encoding of data 失效
标题翻译：数据有效编码的方法和系统
公开(公告)号：US5790057A
公开(公告)日：1998-08-04
申请号：US695885
申请日：1996-08-12
申请人： Yoseph L. Linde , Jeffrey F. Tabor
发明人： Yoseph L. Linde , Jeffrey F. Tabor
IPC分类号： H03M5/16 , H04L1/00
CPC分类号： H04L1/0057 , H03M5/16
摘要： The invention relates to the efficient coding of packetized binary (NRZ) data, for example Ethernet packets, over a binary channel. Since Ethernet packetized data has three states (0, 1, and Idle), the theoretical bandwidth required for transmission, assuming completely random packets of arbitrary length and arbitrary interpacket idle periods, i.e. gaps, is 1.585 the data rate. The invention uses the information that both packets and gaps have predetermined minimum lengths constructs more efficient codes. In particular, a coding scheme is shown that provides in two states signal requiring a bandwidth of only 1.25 the three state signal data rate.
摘要翻译：本发明涉及通过二进制信道对分组二进制（NRZ）数据（例如以太网分组）的有效编码。由于以太网分组化数据具有三种状态（0,1和Idle），所以传输所需的理论带宽是假定任意长度和任意分组空闲周期（即间隙）的完全随机分组是数据速率的1.585。本发明使用分组和间隙具有预定最小长度的信息来构建更有效的代码。特别地，示出了提供两个状态的信号，其需要三个状态信号数据速率仅为1.25的带宽。

3. 发明授权

US4611133A High speed fully precharged programmable logic array 失效
标题翻译：高速全预充电可编程逻辑阵列
公开(公告)号：US4611133A
公开(公告)日：1986-09-09
申请号：US493901
申请日：1983-05-12
申请人： Benjamin C. Peterson , Yoseph L. Linde , Yigal Brandman
发明人： Benjamin C. Peterson , Yoseph L. Linde , Yigal Brandman
IPC分类号： H03K19/177 , H03K19/017 , H03K19/096 , H03K19/20
CPC分类号： H03K19/1772
摘要： A logic array which is small in size and low in power dissipation uses only one clock signal. The array is fully precharged by precharging a first portion and a second portion and then applying ground to the first portion while delayably applying the ground to the second portion. The address is read into the first portion during the precharging to speed up operation of the array.
摘要翻译：体积小，功耗低的逻辑阵列仅使用一个时钟信号。通过对第一部分和第二部分进行预充电然后将接地施加到第一部分同时将接地延伸到第二部分来将阵列完全预充电。在预充电期间将地址读入第一部分以加速阵列的操作。

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