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1. 发明授权

US08530329B2 Methods of fabricating semiconductor devices having various isolation regions 有权
标题翻译：制造具有各种隔离区域的半导体器件的方法
公开(公告)号：US08530329B2
公开(公告)日：2013-09-10
申请号：US13162050
申请日：2011-06-16
申请人： Yong-Soon Choi , Jun-Won Lee , Gil-Heyun Choi , Eun-Kee Hong , Hong-Gun Kim , Ha-Young Yi
发明人： Yong-Soon Choi , Jun-Won Lee , Gil-Heyun Choi , Eun-Kee Hong , Hong-Gun Kim , Ha-Young Yi
IPC分类号： H01L21/78
CPC分类号： H01L21/76229 , H01L21/02222 , H01L21/02271 , H01L21/76885 , H01L27/105 , H01L27/10897 , H01L27/11531 , H01L27/11548
摘要： A method of fabricating a semiconductor device includes forming a first trench and a second trench in a semiconductor substrate, forming a first insulator to completely fill the first trench, the first insulator covering a bottom surface and lower sidewalls of the second trench and exposing upper sidewalls of the second trench, and forming a second insulator on the first insulator in the second trench.
摘要翻译：制造半导体器件的方法包括在半导体衬底中形成第一沟槽和第二沟槽，形成第一绝缘体以完全填充第一沟槽，第一绝缘体覆盖第二沟槽的底表面和下侧壁，并暴露上侧壁并且在所述第二沟槽中的所述第一绝缘体上形成第二绝缘体。

2. 发明申请

US20120034757A1 METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING VARIOUS ISOLATION REGIONS 有权
标题翻译：制备各种分离区域的半导体器件的方法
公开(公告)号：US20120034757A1
公开(公告)日：2012-02-09
申请号：US13162050
申请日：2011-06-16
申请人： Yong-Soon Choi , Jun-Won Lee , Gil-Heyun Choi , Eunkee Hong , Hong-Gun Kim , Ha-Young Yi
发明人： Yong-Soon Choi , Jun-Won Lee , Gil-Heyun Choi , Eunkee Hong , Hong-Gun Kim , Ha-Young Yi
IPC分类号： H01L21/762
CPC分类号： H01L21/76229 , H01L21/02222 , H01L21/02271 , H01L21/76885 , H01L27/105 , H01L27/10897 , H01L27/11531 , H01L27/11548
摘要： A method of fabricating a semiconductor device includes forming a first trench and a second trench in a semiconductor substrate, forming a first insulator to completely fill the first trench, the first insulator covering a bottom surface and lower sidewalls of the second trench and exposing upper sidewalls of the second trench, and forming a second insulator on the first insulator in the second trench.
摘要翻译：制造半导体器件的方法包括在半导体衬底中形成第一沟槽和第二沟槽，形成第一绝缘体以完全填充第一沟槽，第一绝缘体覆盖第二沟槽的底表面和下侧壁，并暴露上侧壁并且在所述第二沟槽中的所述第一绝缘体上形成第二绝缘体。

3. 发明授权

US08043914B2 Methods of fabricating flash memory devices comprising forming a silicide on exposed upper and side surfaces of a control gate 有权
标题翻译：制造闪存器件的方法包括在暴露的控制栅极的上表面和侧表面上形成硅化物
公开(公告)号：US08043914B2
公开(公告)日：2011-10-25
申请号：US12629920
申请日：2009-12-03
申请人： Jong-wan Choi , Yong-soon Choi , Bo-young Lee , Eunkee Hong , Eun-kyung Baek , Ju-seon Goo
发明人： Jong-wan Choi , Yong-soon Choi , Bo-young Lee , Eunkee Hong , Eun-kyung Baek , Ju-seon Goo
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/11524
摘要： Provided are methods of fabricating flash memory devices that may prevent a short circuit from occurring between cell gate lines. Methods of fabricating such flash memory devices may include forming gate lines including a series of multiple cell gate lines and multiple selection gate lines. Each gate line may include a stacked structure of a tunnel insulating layer, a floating gate, a gate insulating layer, and/or a polysilicon layer operable to be a control gate, all formed on a semiconductor substrate. Methods may include forming a first insulating layer that selectively fills gaps between the cell gate lines from the bottom up and between adjacent ones of the cell gate lines and the selection gate lines, and does not fill a space located on outer sides of the selection gate lines that are opposite the plurality of cell gate lines. A spacer may be formed on the outer sides of the selection gate lines that are opposite to the cell gate lines, after forming the first insulating layer. A second insulating layer may be formed in a space where the spacer is formed.
摘要翻译：提供了制造闪存器件的方法，其可以防止在单元栅极线之间发生短路。制造这种闪存器件的方法可以包括形成包括一系列多单元栅极线和多个选择栅极线的栅极线。每个栅极线可以包括全部形成在半导体衬底上的隧道绝缘层，浮动栅极，栅极绝缘层和/或可操作为控制栅极的多晶硅层的堆叠结构。方法可以包括形成第一绝缘层，其选择性地从底部向上和相邻的单元栅极线和选择栅极线之间填充单元栅极线之间的间隙，并且不填充位于选择栅极的外侧的空间与多个单元栅极线相对的线。在形成第一绝缘层之后，可以在选择栅极线的与单元栅极线相对的外侧上形成间隔物。可以在形成间隔物的空间中形成第二绝缘层。

4. 发明申请

US20080121977A1 Semiconductor device and method of manufacturing having the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080121977A1
公开(公告)日：2008-05-29
申请号：US11699419
申请日：2007-01-30
申请人： Yong-Soon Choi , Hong-Gun Kim , Jong-Wan Choi , Eun-Kyung Baek , Ju-Seon Goo
发明人： Yong-Soon Choi , Hong-Gun Kim , Jong-Wan Choi , Eun-Kyung Baek , Ju-Seon Goo
IPC分类号： H01L29/788 , H01L21/04
CPC分类号： H01L21/76224 , H01L27/11521 , H01L29/7881
摘要： A semiconductor device includes a substrate having a trench, a liner layer pattern on sidewalls and a bottom surface of the trench, the liner layer pattern including a first oxide layer pattern and a second oxide layer pattern, a diffusion blocking layer pattern on the liner layer pattern, and an isolation layer pattern in the trench on the diffusion blocking layer pattern.
摘要翻译：半导体器件包括具有沟槽的衬底，侧壁上的衬垫层图案和沟槽的底表面，衬里层图案包括第一氧化物层图案和第二氧化物层图案，衬垫层上的扩散阻挡层图案图案和扩散阻挡层图案上的沟槽中的隔离层图案。

5. 发明申请

US20080014711A1 Semiconductor device isolation structures and methods of fabricating such structures 有权
标题翻译：半导体器件隔离结构及其制造方法
公开(公告)号：US20080014711A1
公开(公告)日：2008-01-17
申请号：US11654588
申请日：2007-01-18
申请人： Jong-Wan Choi , Ju-Seon Goo , Hong-Gun Kim , Yong-Soon Choi , Sung-Tae Kim , Eun-Kyung Baek
发明人： Jong-Wan Choi , Ju-Seon Goo , Hong-Gun Kim , Yong-Soon Choi , Sung-Tae Kim , Eun-Kyung Baek
IPC分类号： H01L21/76
CPC分类号： H01L21/76229 , H01L27/105 , H01L27/11531
摘要： Disclosed are methods for fabricating semiconductor devices incorporating a composite trench isolation structure comprising a first oxide pattern, a SOG pattern and a second oxide pattern wherein the oxide patterns enclose the SOG pattern. The methods include the deposition of a first oxide layer and a SOG layer to fill recessed trench regions formed in the substrate. The first oxide layer and the SOG layer are then subjected to a planarization sequence including a CMP process followed by an etchback process to form a composite structure having a substantially flat upper surface that exposes both the oxide and the SOG material. The second oxide layer is then applied and subjected to a similar CMP/etchback sequence to obtain a composite structure having an upper surface that is recessed relative to a plane defined by the surfaces of adjacent active regions.
摘要翻译：公开了用于制造半导体器件的方法，该半导体器件结合有包括第一氧化物图案，SOG图案和第二氧化物图案的复合沟槽隔离结构，其中氧化物图案包围SOG图案。所述方法包括沉积第一氧化物层和SOG层以填充形成在衬底中的凹陷沟槽区域。然后对第一氧化物层和SOG层进行包括CMP工艺的随后的回蚀工艺的平坦化顺序，以形成具有露出氧化物和SOG材料的基本上平坦的上表面的复合结构。然后施加第二氧化物层并进行类似的CMP /回蚀序列以获得具有相对于由相邻有源区的表面限定的平面凹进的上表面的复合结构。

6. 发明申请

US20050277265A1 Methods of forming trench isolation layers using high density plasma chemical vapor deposition 有权
标题翻译：使用高密度等离子体化学气相沉积形成沟槽隔离层的方法
公开(公告)号：US20050277265A1
公开(公告)日：2005-12-15
申请号：US11149307
申请日：2005-06-09
申请人： Yong-Won Cha , Kyu-Tae Na , Yong-Soon Choi , Eunkee Hong , Ju-Seon Goo
发明人： Yong-Won Cha , Kyu-Tae Na , Yong-Soon Choi , Eunkee Hong , Ju-Seon Goo
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76224
摘要： A method of forming a trench isolation layer can include forming an isolation layer in a trench using High Density Plasma Chemical Vapor Deposition (HDPCVD) with a carrier gas comprising hydrogen. Other methods are disclosed.
摘要翻译：形成沟槽隔离层的方法可以包括使用具有包含氢的载气的高密度等离子体化学气相沉积（HDPCVD）在沟槽中形成隔离层。公开了其他方法。

7. 发明申请

US20110037109A1 SEMICONDUCTOR DEVICES INCLUDING LOWER AND UPPER DEVICE ISOLATION PATTERNS 审中-公开
标题翻译：半导体器件，包括下部和上部器件隔离图案
公开(公告)号：US20110037109A1
公开(公告)日：2011-02-17
申请号：US12910552
申请日：2010-10-22
申请人： Hong-Gun KIM , Ju-Seon GOO , Mun-Jun KIM , Yong-Soon CHOI , Sung-Tae KIM , Eun-Kyung BAEK
发明人： Hong-Gun KIM , Ju-Seon GOO , Mun-Jun KIM , Yong-Soon CHOI , Sung-Tae KIM , Eun-Kyung BAEK
IPC分类号： H01L29/68
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： In some embodiments, a semiconductor substrate includes trenches defining active regions. The semiconductor device further includes lower and upper device isolation patterns disposed in the trenches. An intergate insulation pattern and a control gate electrode are disposed on the semiconductor substrate to cross over the active regions. A charge storage electrode is between the control gate electrode and the active regions. A gate insulation pattern is between the charge storage electrode and the active regions, and the intergate insulation pattern directly contacts the upper device isolation pattern between the active regions.
摘要翻译：在一些实施例中，半导体衬底包括限定有源区的沟槽。半导体器件还包括设置在沟槽中的下部和上部器件隔离图案。栅极绝缘图案和控制栅电极设置在半导体衬底上以跨越有源区。电荷存储电极位于控制栅电极和有源区之间。栅极绝缘图案位于电荷存储电极和有源区之间，并且栅间绝缘图案直接接触有源区之间的上部器件隔离图案。

8. 发明授权

US07674685B2 Semiconductor device isolation structures and methods of fabricating such structures 有权
标题翻译：半导体器件隔离结构及其制造方法
公开(公告)号：US07674685B2
公开(公告)日：2010-03-09
申请号：US11654588
申请日：2007-01-18
申请人： Jong-Wan Choi , Ju-Seon Goo , Hong-Gun Kim , Yong-Soon Choi , Sung-Tae Kim , Eun-Kyung Baek
发明人： Jong-Wan Choi , Ju-Seon Goo , Hong-Gun Kim , Yong-Soon Choi , Sung-Tae Kim , Eun-Kyung Baek
IPC分类号： H01L21/76
CPC分类号： H01L21/76229 , H01L27/105 , H01L27/11531
摘要： Disclosed are methods for fabricating semiconductor devices incorporating a composite trench isolation structure comprising a first oxide pattern, a SOG pattern and a second oxide pattern wherein the oxide patterns enclose the SOG pattern. The methods include the deposition of a first oxide layer and a SOG layer to fill recessed trench regions formed in the substrate. The first oxide layer and the SOG layer are then subjected to a planarization sequence including a CMP process followed by an etchback process to form a composite structure having a substantially flat upper surface that exposes both the oxide and the SOG material. The second oxide layer is then applied and subjected to a similar CMP/etchback sequence to obtain a composite structure having an upper surface that is recessed relative to a plane defined by the surfaces of adjacent active regions.
摘要翻译：公开了用于制造半导体器件的方法，该半导体器件结合有包括第一氧化物图案，SOG图案和第二氧化物图案的复合沟槽隔离结构，其中氧化物图案包围SOG图案。所述方法包括沉积第一氧化物层和SOG层以填充形成在衬底中的凹陷沟槽区域。然后对第一氧化物层和SOG层进行包括CMP工艺的随后的回蚀工艺的平坦化顺序，以形成具有露出氧化物和SOG材料的基本上平坦的上表面的复合结构。然后施加第二氧化物层并进行类似的CMP /回蚀序列以获得具有相对于由相邻有源区的表面限定的平面凹进的上表面的复合结构。

9. 发明申请

US20080206954A1 METHODS OF REDUCING IMPURITY CONCENTRATION IN ISOLATING FILMS IN SEMICONDUCTOR DEVICES 有权
标题翻译：降低半导体器件隔离膜中污染浓度的方法
公开(公告)号：US20080206954A1
公开(公告)日：2008-08-28
申请号：US12038278
申请日：2008-02-27
申请人： Jong-wan Choi , Eun-kyung Baek , Sang-hoon Ahn , Hong-gun Kim , Dong-chul Suh , Yong-soon Choi
发明人： Jong-wan Choi , Eun-kyung Baek , Sang-hoon Ahn , Hong-gun Kim , Dong-chul Suh , Yong-soon Choi
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L21/823481
摘要： A method of fabricating a semiconductor device includes forming a lower device on a lower semiconductor substrate, and forming an interlayer insulating film on the lower device. An upper semiconductor substrate is formed on the interlayer insulating film such that the interlayer insulating film is between the lower and upper semiconductor substrates. Upper trenches are formed within the upper semiconductor substrate. An upper device isolating film is formed within the upper trenches. The upper device isolating film is irradiated with ultraviolet light having a wavelength configured to break chemical bonds of impurities in the upper device isolating film to reduce an impurity concentration thereof.
摘要翻译：制造半导体器件的方法包括在下半导体衬底上形成下部器件，并在下部器件上形成层间绝缘膜。在层间绝缘膜上形成上半导体衬底，使得层间绝缘膜位于下半导体衬底和上半导体衬底之间。上沟槽形成在上半导体衬底内。上部器件隔离膜形成在上部沟槽内。用上述器件隔离膜中的杂质化学键的波长的紫外线照射上部器件隔离膜以降低其杂质浓度。

10. 发明授权

US07332409B2 Methods of forming trench isolation layers using high density plasma chemical vapor deposition 有权
标题翻译：使用高密度等离子体化学气相沉积形成沟槽隔离层的方法
公开(公告)号：US07332409B2
公开(公告)日：2008-02-19
申请号：US11149307
申请日：2005-06-09
申请人： Yong-Won Cha , Kyu-Tae Na , Yong-Soon Choi , Eunkee Hong , Ju-Seon Goo
发明人： Yong-Won Cha , Kyu-Tae Na , Yong-Soon Choi , Eunkee Hong , Ju-Seon Goo
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： A method of forming a trench isolation layer can include forming an isolation layer in a trench using High Density Plasma Chemical Vapor Deposition (HDPCVD) with a carrier gas comprising hydrogen. Other methods are disclosed.
摘要翻译：形成沟槽隔离层的方法可以包括使用具有包含氢的载气的高密度等离子体化学气相沉积（HDPCVD）在沟槽中形成隔离层。公开了其他方法。

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