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1. 发明授权

US10369494B2 Salt production automation system utilizing three-dimensionally structured evaporation fields 有权
公开(公告)号：US10369494B2
公开(公告)日：2019-08-06
申请号：US15535872
申请日：2015-11-06
申请人： Yong Hee Park
发明人： Yong Hee Park
IPC分类号： B01D9/00 , C02F1/14 , C01D3/06 , A23L27/40 , C02F103/08
摘要： Provided a salt production automation system utilizing three-dimensionally structured evaporation fields. The salt production automation system utilizing three-dimensionally structured evaporation fields includes: evaporation fields which have collection pools (SWT) and are installed in at least two separate places; a plurality of evaporation members which are three-dimensionally arranged in the evaporation fields to make seawater flow downwards; and a seawater supply unit which supplies seawater to the evaporation members so that seawater can flow downwards from the evaporation members, wherein among the evaporation fields, the number of evaporation members gradually decreases from the first stage evaporation field to the final stage evaporation field.

2. 发明申请

US20160114258A1 HIGHLY EFFICIENT SEA WATER EVAPORATOR, AND EVAPORATION ROPE MODULE 审中-公开
标题翻译：高效率的海水蒸发器和蒸发杯模块
公开(公告)号：US20160114258A1
公开(公告)日：2016-04-28
申请号：US14775857
申请日：2013-12-06
申请人： Yong Hee PARK
发明人： Yong Hee PARK
IPC分类号： B01D1/00 , B01D1/30 , C02F1/14 , B01D1/24
CPC分类号： B01D1/0035 , B01D1/16 , B01D1/18 , B01D1/24 , B01D1/30 , C01D3/06 , C02F1/14 , C02F2103/08 , Y02A20/128 , Y02A20/141 , Y02A20/212
摘要： High efficiency seawater evaporation apparatus comprises showering unit installed at the saltpan; and evaporation rope module wherein multiple evaporation ropes are collected in group by the holder and the respective evaporation modules are extended along the upper and lower direction in the state each other separated in a predetermined interval and wherein, when the seawater is supplied to the respective evaporation ropes by the showering unit, the seawater may flow down along the surface of the respective evaporation ropes and the evaporation of the seawater may be accelerated.
摘要翻译：高效海水蒸发装置包括安装在盐水处的淋浴装置; 和蒸发绳组件，其中多个蒸发绳由保持器组集中，并且相应的蒸发模块沿着上下方向延伸，彼此以预定间隔分开，并且其中当将海水供应到相应的蒸发绳索可以沿着相应蒸发绳索的表面向下流动，并且可以加速海水的蒸发。

3. 发明授权

US08563197B2 Methods, apparatus and computer program products for fabricating masks and semiconductor devices using model-based optical proximity effect correction and lithography-friendly layout 有权
标题翻译：使用基于模型的光学邻近效应校正和光刻友好布局制造掩模和半导体器件的方法，装置和计算机程序产品
公开(公告)号：US08563197B2
公开(公告)日：2013-10-22
申请号：US12238884
申请日：2008-09-26
申请人： Sung-soo Suh , Suk-joo Lee , Yong-hee Park , Mi-kyeong Lee
发明人： Sung-soo Suh , Suk-joo Lee , Yong-hee Park , Mi-kyeong Lee
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： Design rules for circuit patterns of a semiconductor device are identified, and schematic layouts of the circuit patterns are generated according to the design rules. Lithography friendly layout (LFL) circuit patterns are generated from the schematic layouts. Target layout circuit patterns are generated from the LFL circuit patterns. Optical proximity effect correction (OPC) is performed on the target layout circuit patterns to generate OPC circuit patterns. A mask is fabricated from the OPC circuit patterns, and may be used fabricate a semiconductor device.
摘要翻译：识别半导体器件的电路图案的设计规则，根据设计规则生成电路图案的原理图布局。从原理图布局生成光刻友好布局（LFL）电路图案。目标布局电路图案是从LFL电路图形生成的。对目标布局电路图案执行光学邻近效应校正（OPC）以产生OPC电路图案。掩模由OPC电路图形制成，可用于制造半导体器件。

4. 发明申请

US20110237005A1 Layout Testing Method and Wafer Manufacturing Method 有权
标题翻译：布局测试方法和晶圆制造方法
公开(公告)号：US20110237005A1
公开(公告)日：2011-09-29
申请号：US13050276
申请日：2011-03-17
申请人： Daewook Kim , Yong Hee Park , Ji-Seong Doh
发明人： Daewook Kim , Yong Hee Park , Ji-Seong Doh
IPC分类号： H01L21/66 , G06F17/50
CPC分类号： G06F17/5081 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A product layout testing method includes testing and correcting one or more patterns of a product layout, detecting and correcting electrical characteristic changes of transistors of the product layout, and testing whether a product characteristic predicted from the product layout is equal to that predicted from a designed circuit view. Weak points with respect to the pattern may be detected and corrected, electrical characteristic changes depending on layout parameters may be detected and corrected, and whether a circuit operation depending on parasitic components is normal may be checked.
摘要翻译：产品布局测试方法包括测试和校正产品布局的一个或多个图案，检测和校正产品布局的晶体管的电特性变化，以及测试从产品布局预测的产品特性是否等于从设计电路图。可以检测和校正关于图案的弱点，可以检测和校正根据布局参数的电特性变化，以及根据寄生成分的电路操作是否正常。

5. 发明授权

US08356271B2 Layout testing method and wafer manufacturing method 有权
标题翻译：布局测试方法和晶圆制造方法
公开(公告)号：US08356271B2
公开(公告)日：2013-01-15
申请号：US13050276
申请日：2011-03-17
申请人： Daewook Kim , Yong Hee Park , Ji-Seong Doh
发明人： Daewook Kim , Yong Hee Park , Ji-Seong Doh
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A product layout testing method includes testing and correcting one or more patterns of a product layout, detecting and correcting electrical characteristic changes of transistors of the product layout, and testing whether a product characteristic predicted from the product layout is equal to that predicted from a designed circuit view. Weak points with respect to the pattern may be detected and corrected, electrical characteristic changes depending on layout parameters may be detected and corrected, and whether a circuit operation depending on parasitic components is normal may be checked.
摘要翻译：产品布局测试方法包括测试和校正产品布局的一个或多个图案，检测和校正产品布局的晶体管的电特性变化，以及测试从产品布局预测的产品特性是否等于从设计电路图。可以检测和校正关于图案的弱点，可以检测和校正根据布局参数的电特性变化，以及根据寄生成分的电路操作是否正常。

6. 发明申请

US20090087758A1 METHODS, APPARATUS AND COMPUTER PROGRAM PRODUCTS FOR FABRICATING MASKS AND SEMICONDUCTOR DEVICES USING MODEL-BASED OPTICAL PROXIMITY EFFECT CORRECTION AND LITHOGRAPHY-FRIENDLY LAYOUT 有权
标题翻译：使用基于模型的光学近似效应校正和平滑友好布局的方法，装置和计算机程序产品来制作掩模和半导体器件
公开(公告)号：US20090087758A1
公开(公告)日：2009-04-02
申请号：US12238884
申请日：2008-09-26
申请人： Sung-soo Suh , Suk-joo Lee , Yong-hee Park , Mi-kyeong Lee
发明人： Sung-soo Suh , Suk-joo Lee , Yong-hee Park , Mi-kyeong Lee
IPC分类号： G03F7/20 , G03F1/00
CPC分类号： G03F1/36
摘要： Design rules for circuit patterns of a semiconductor device are identified, and schematic layouts of the circuit patterns are generated according to the design rules. Lithography friendly layout (LFL) circuit patterns are generated from the schematic layouts. Target layout circuit patterns are generated from the LFL circuit patterns. Optical proximity effect correction (OPC) is performed on the target layout circuit patterns to generate OPC circuit patterns. A mask is fabricated from the OPC circuit patterns, and may be used fabricate a semiconductor device.
摘要翻译：识别半导体器件的电路图案的设计规则，根据设计规则生成电路图案的原理图布局。从原理图布局生成光刻友好布局（LFL）电路图案。目标布局电路图案是从LFL电路图形生成的。对目标布局电路图案执行光学邻近效应校正（OPC）以产生OPC电路图案。掩模由OPC电路图形制成，可用于制造半导体器件。

7. 发明申请

US20080052660A1 METHOD OF CORRECTING A DESIGNED PATTERN OF A MASK 审中-公开
标题翻译：校正设计图案的方法
公开(公告)号：US20080052660A1
公开(公告)日：2008-02-28
申请号：US11830265
申请日：2007-07-30
申请人： Woo-seok SHIM , Moon-Hyun YOO , Chun-Suk SUH , Jung-Hyeon LEE , Ji-Suk HONG , Yong-Hee PARK
发明人： Woo-seok SHIM , Moon-Hyun YOO , Chun-Suk SUH , Jung-Hyeon LEE , Ji-Suk HONG , Yong-Hee PARK
IPC分类号： G03F1/00 , G06F17/50
CPC分类号： G03F1/36
摘要： A method of correcting a design pattern of a mask takes into account the overlay margin between adjacent one of actual patterns that are stacked on a substrate. First, a pattern of a photomask for forming a first one of the actual patterns on a substrate is conceived. Also, information representing the image of a second one of the actual patterns is produced. Then, optical proximity correction (OPC) is performed on the first pattern based on the information. The information may be obtained by simulating the transcription of a photomask having a second pattern designed to form the second actual pattern, or by forming the second actual pattern and then capturing the image of the second actual pattern. Accordingly, a sufficient margin is provided between the second actual pattern and the first pattern on which the optical proximity correction has been performed.
摘要翻译：校正掩模的设计图案的方法考虑了堆叠在基板上的相邻的一个实际图案之间的覆盖边缘。首先，设想用于在基板上形成第一种实际图案的光掩模图案。此外，产生表示第二实际图案的图像的信息。然后，基于该信息对第一图案执行光学邻近校正（OPC）。可以通过模拟具有被设计为形成第二实际图案的第二图案的光掩模的转录或通过形成第二实际图案然后捕获第二实际图案的图像来获得信息。因此，在第二实际图案和已进行光学邻近校正的第一图案之间提供足够的余量。

8. 发明授权

US10376808B2 Sea water evaporator, and evaporation rope module for salt production 有权
公开(公告)号：US10376808B2
公开(公告)日：2019-08-13
申请号：US14775857
申请日：2013-12-06
申请人： Yong Hee Park
发明人： Yong Hee Park
IPC分类号： B01D1/00 , B01D1/16 , C01D3/06 , C02F1/14 , B01D1/24 , B01D1/30 , B01D1/18 , C02F103/08
摘要： High efficiency seawater evaporation apparatus comprises showering unit installed at the saltpan; and evaporation rope module wherein multiple evaporation ropes are collected in group by the holder and the respective evaporation modules are extended along the upper and lower direction in the state each other separated in a predetermined interval and wherein, when the seawater is supplied to the respective evaporation ropes by the showering unit, the seawater may flow down along the surface of the respective evaporation ropes and the evaporation of the seawater may be accelerated.

9. 发明申请

US20180021694A1 SALT PRODUCTION AUTOMATION SYSTEM UTILIZING THREE-DIMENSIONALLY STRUCTURED EVAPORATION FIELDS 审中-公开
公开(公告)号：US20180021694A1
公开(公告)日：2018-01-25
申请号：US15535872
申请日：2015-11-06
申请人： Yong Hee PARK
发明人： Yong Hee PARK
IPC分类号： B01D9/00 , A23L27/40 , C01D3/06
CPC分类号： B01D9/0018 , A23L27/40 , A23V2002/00 , B01D9/0059 , B01D2009/0086 , C01D3/06 , C02F1/14 , C02F2103/08 , Y02A20/128 , Y02A20/212 , Y02W10/37
摘要： Provided a salt production automation system utilizing three-dimensionally structured evaporation fields. The salt production automation system utilizing three-dimensionally structured evaporation fields includes: evaporation fields which have collection pools (SWT) and are installed in at least two separate places; a plurality of evaporation members which are three-dimensionally arranged in the evaporation fields to make seawater flow downwards; and a seawater supply unit which supplies seawater to the evaporation members so that seawater can flow downwards from the evaporation members, wherein among the evaporation fields, the number of evaporation members gradually decreases from the first stage evaporation field to the final stage evaporation field.

10. 发明申请

US20160079354A1 INTEGRATED CIRCUIT DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：集成电路装置及其制造方法
公开(公告)号：US20160079354A1
公开(公告)日：2016-03-17
申请号：US14807912
申请日：2015-07-24
申请人： Yong-hee Park , Young-seok Song , Ji-soo Chang , Young-chul Hwang
发明人： Yong-hee Park , Young-seok Song , Ji-soo Chang , Young-chul Hwang
IPC分类号： H01L29/06 , H01L23/535 , H01L27/088
CPC分类号： H01L29/7856 , H01L21/823431 , H01L21/823437 , H01L27/0886 , H01L27/0924 , H01L29/66545
摘要： An IC device includes a substrate including a device region having a fin-type active region and a deep trench region; a gate line that extends in a direction intersecting the fin-type active region; and an inter-device isolation layer that fills the deep trench region. The gate line includes a first gate portion that extends on the device region to cover the fin-type active region and has a flat upper surface at a first level and a second gate portion that extends on the deep trench region to cover the inter-device isolation layer while being integrally connected to the first gate portion and has an upper surface at a second level that is closer to the substrate than the first level.
摘要翻译： IC器件包括：衬底，其包括具有鳍型有源区和深沟槽区的器件区; 栅极线，其在与鳍式有源区域相交的方向上延伸; 以及填充深沟槽区域的器件间隔离层。栅极线包括第一栅极部分，其在器件区域上延伸以覆盖鳍状有源区并且具有处于第一电平的平坦上表面和在深沟槽区域上延伸以覆盖器件间的第二栅极部分隔离层，同时整体连接到第一栅极部分，并且具有比第一电平更靠近基板的第二电平的上表面。

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