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    • 2. 发明授权
    • Multiport memory, data processor and data processing system
    • 多端口存储器,数据处理器和数据处理系统
    • US06480947B1
    • 2002-11-12
    • US09353367
    • 1999-07-15
    • Masami HasegawaYoichi SatohYuuji YanagisawaYoshio IiokaYoshimi KitagawaMakio Uchida
    • Masami HasegawaYoichi SatohYuuji YanagisawaYoshio IiokaYoshimi KitagawaMakio Uchida
    • G06F1200
    • G11C7/1075G06F13/1689Y02D10/14
    • A multiport memory has a plurality of RAMs and a port expansion unit electrically connected to access ports of the RAMs. The port expansion unit includes an input circuit which allows access control information for activating the RAMs in parallel every memory cycles to be collectively inputted thereto by a plurality of memory cycles, a timing generator which generates internal clock signals capable of serially prescribing each memory cycle plural times during one cycle of a clock signal (ck), and a logic circuit capable of sequentially supplying the access control information inputted to the input circuit to the plurality of RAMs in parallel in parts every serial memory cycles synchronized with the internal clock signals. The port expansion unit allows access to the access ports with the plurality of RAMs as a single multiport memory apparently.
    • 多端口存储器具有电连接到RAM的访问端口的多个RAM和端口扩展单元。 端口扩展单元包括:输入电路,其允许用于每个存储周期并行地激活RAM的访问控制信息,以通过多个存储周期共同输入;定时发生器,其产生能够串行地规定每个存储周期的内部时钟信号 时钟信号(ck)的一个周期的逻辑电路,以及逻辑电路,其能够在与内部时钟信号同步的每个串行存储器循环中以部分顺序地将输入到输入电路的访问控制信息并行地分配给多个RAM。 端口扩展单元允许访问具有多个RAM的访问端口作为单个多端口存储器。