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1. 发明申请

US20110208983A1 SUBSTRATE BIAS SWITCHING UNIT FOR A LOW POWER PROCESSOR 有权
标题翻译：用于低功率处理器的基板偏置开关单元
公开(公告)号：US20110208983A1
公开(公告)日：2011-08-25
申请号：US13101678
申请日：2011-05-05
申请人： Yonetaro TOTSUKA , Koichiro ISHIBASHI , Hiroyuki MIZUNO , Osamu Nishii , Kunio UCHIYAMA , Takanori SHIMURA , Asako SEKINE , Yoichi KATSUKI , Susumu NARITA
发明人： Yonetaro TOTSUKA , Koichiro ISHIBASHI , Hiroyuki MIZUNO , Osamu Nishii , Kunio UCHIYAMA , Takanori SHIMURA , Asako SEKINE , Yoichi KATSUKI , Susumu NARITA
IPC分类号： G06F1/26
CPC分类号： G06F1/3296 , G06F1/3203 , Y02D10/172 , Y02D50/20
摘要： The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.
摘要翻译：本发明的特征在于：处理器主电路，用于在处理器芯片上执行程序指令串; 衬底偏置切换单元，用于切换施加到处理器主电路的衬底的衬底偏压的电压; 以及操作模式控制单元，用于响应于执行处理器主电路中的待机模式的指令，控制所述衬底偏置切换单元，使得所述偏置切换到所述处理器主电路的电压待机模式，并且为了响应于来自外部的待机释放的中断来控制衬底偏置切换单元，使得偏置被切换到用于正常模式的电压，并且还用于释放在切换到其上的偏置电压已经稳定之后，处理器主电路的待机重新开始操作。

2. 发明申请

US20100005324A1 SUBSTRATE BIAS SWITCHING UNIT FOR A LOW POWER PROCESSOR 失效
标题翻译：用于低功率处理器的基板偏置开关单元
公开(公告)号：US20100005324A1
公开(公告)日：2010-01-07
申请号：US12346268
申请日：2008-12-30
申请人： Yonetaro TOTSUKA , Koichiro Ishibashi , Hiroyuki Mizuno , Osamu Nishii , Kunio Uchiyama , Takanori Shimura , Asako Sekine , Yoichi Katsuki , Susumu Narita
发明人： Yonetaro TOTSUKA , Koichiro Ishibashi , Hiroyuki Mizuno , Osamu Nishii , Kunio Uchiyama , Takanori Shimura , Asako Sekine , Yoichi Katsuki , Susumu Narita
IPC分类号： G06F1/26
CPC分类号： G06F1/3296 , G06F1/3203 , Y02D10/172 , Y02D50/20
摘要： The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.
摘要翻译：本发明的特征在于：处理器主电路，用于在处理器芯片上执行程序指令串; 衬底偏置切换单元，用于切换施加到处理器主电路的衬底的衬底偏压的电压; 以及操作模式控制单元，用于响应于执行处理器主电路中的待机模式的指令，控制所述衬底偏置切换单元，使得所述偏置切换到所述处理器主电路的电压待机模式，并且为了响应于来自外部的待机释放的中断来控制衬底偏置切换单元，使得偏置被切换到用于正常模式的电压，并且还用于释放在切换到其上的偏置电压已经稳定之后，处理器主电路的待机重新开始操作。

3. 发明授权

US07958379B2 Substrate bias switching unit for a low power processor 失效
标题翻译：用于低功耗处理器的基板偏置开关单元
公开(公告)号：US07958379B2
公开(公告)日：2011-06-07
申请号：US12346268
申请日：2008-12-30
申请人： Yonetaro Totsuka , Koichiro Ishibashi , Hiroyuki Mizuno , Osamu Nishii , Kunio Uchiyama , Takanori Shimura , Asako Sekine , Yoichi Katsuki , Susumu Narita
发明人： Yonetaro Totsuka , Koichiro Ishibashi , Hiroyuki Mizuno , Osamu Nishii , Kunio Uchiyama , Takanori Shimura , Asako Sekine , Yoichi Katsuki , Susumu Narita
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32 , B23K11/24
CPC分类号： G06F1/3296 , G06F1/3203 , Y02D10/172 , Y02D50/20
摘要： The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.
摘要翻译：本发明的特征在于：处理器主电路，用于在处理器芯片上执行程序指令串; 衬底偏置切换单元，用于切换施加到处理器主电路的衬底的衬底偏压的电压; 以及操作模式控制单元，用于响应于执行处理器主电路中的待机模式的指令，控制所述衬底偏置切换单元，使得所述偏置切换到所述处理器主电路的电压待机模式，并且为了响应于来自外部的待机释放的中断来控制衬底偏置切换单元，使得偏置被切换到用于正常模式的电压，并且还用于释放在切换到其上的偏置电压已经稳定之后，处理器主电路的待机重新开始操作。

4. 发明授权

US07289802B2 Communication terminal performance measurement system having effective trace information display function and communication terminal performance measurement method 有权
标题翻译：通信终端性能测量系统具有有效的跟踪信息显示功能和通信终端性能测量方法
公开(公告)号：US07289802B2
公开(公告)日：2007-10-30
申请号：US10554568
申请日：2005-02-28
申请人： Shoichi Nakamura , Tsuyoshi Sato , Hiroyuki Tsuda , Tsutomu Tokuke , Hiroki Shiina , Takashi Sakamoto , Yoichi Katsuki
发明人： Shoichi Nakamura , Tsuyoshi Sato , Hiroyuki Tsuda , Tsutomu Tokuke , Hiroki Shiina , Takashi Sakamoto , Yoichi Katsuki
IPC分类号： H04Q7/20 , H04B1/38 , H04B7/00 , H04M1/29
CPC分类号： H04W24/06
摘要： An acquisition section acquires trace information including a plurality of log information having information on contents and types of log information based on message information of test signals transmitted to a communication terminal and a series of reply signals from the communication terminals, and provides clock time information at which the respective message information have been acquired. The trace information including the plurality of log information, is displayed in predetermined formats. An indication bar display section displays an indication bar on which the plurality of log information are arranged in a time series based on the clock time at which the respective message information have been acquired. A log sequence display section displays a predetermined number of log information as log sequences having time stamps based on the clock time information at which the respective log information have been acquired, so as to be associated with the indication bar.
摘要翻译：采集单元基于发送给通信终端的测试信号的消息信息和来自通信终端的一系列应答信号，获取包括具有关于内容和日志信息类型的信息的多个日志信息的跟踪信息，并且提供时钟信息哪个已经获取了相应的消息信息。包括多个日志信息的跟踪信息以预定格式显示。指示条显示部分基于已经获取相应消息信息的时钟时间，以时间序列显示多个日志信息在其上排列的指示栏。日志序列显示部分基于已经获取了各个日志信息的时钟时间信息，将预定数量的日志信息显示为具有时间戳的日志序列，以便与指示条相关联。

5. 发明申请

US20060270398A1 Communication terminal performance measurement system having effective trace information display function and communication terminal performance measurement method 有权
标题翻译：通信终端性能测量系统具有有效的跟踪信息显示功能和通信终端性能测量方法
公开(公告)号：US20060270398A1
公开(公告)日：2006-11-30
申请号：US10554568
申请日：2005-02-28
申请人： Shoichi Nakamura , Tsuyoshi Sato , Hiroyuki Tsuda , Tsutomu Tokuke , Hiroki Shiina , Takashi Sakamoto , Yoichi Katsuki
发明人： Shoichi Nakamura , Tsuyoshi Sato , Hiroyuki Tsuda , Tsutomu Tokuke , Hiroki Shiina , Takashi Sakamoto , Yoichi Katsuki
IPC分类号： H04Q7/20 , H04B17/00
CPC分类号： H04W24/06
摘要： A trace information acquisition section acquires trace information including a plurality of log information which have information on contents and types of log information based on predetermined message information of each of a series of test signals transmitted to a communication terminal for being evaluated by a communication terminal test measuring instrument and a series of reply signals from the communication terminal for being evaluated received by the communication terminal test measuring instrument, and provides clock time information at which the respective message information have been acquired. A trace information display processing control section displays the trace information including the plurality of log information in predetermined formats. The trace information display processing control section has an indication bar display section which displays an indication bar on which the plurality of log information are arranged in a time series based on the clock time at which the respective message information have been acquired so as to be identifiable by being sorted in accordance with the types of the predetermined message information, and a log sequence display section which displays a predetermined number of log information among the plurality of log information as log sequences having time stamps based on the clock time information at which the respective log information have been acquired so as to be associated with the indication bar.
摘要翻译：跟踪信息获取部基于通过发送给通信终端的一系列测试信号中的每一个的预定消息信息，通过通信终端测试来评估包括具有关于日志信息的内容和类型的信息的多个日志信息测量仪器和来自通信终端的一系列应答信号，用于由通信终端测试仪器接收评估，并且提供已经获取了各个消息信息的时钟时间信息。跟踪信息显示处理控制部分以预定格式显示包括多个日志信息的跟踪信息。跟踪信息显示处理控制部分具有指示条显示部分，其基于已经获取相应消息信息的时钟时间，以时间序列显示多个日志信息在其上的指示条，以便被识别通过根据预定消息信息的类型进行排序，以及日志序列显示部分，其在多个日志信息中显示预定数量的日志信息，作为具有时间戳的日志序列，其中基于时间信息，已经获取日志信息以便与指示栏相关联。

6. 发明授权

US08364988B2 Substrate bias switching unit for a low power processor 有权
公开(公告)号：US08364988B2
公开(公告)日：2013-01-29
申请号：US13101678
申请日：2011-05-05
申请人： Yonetaro Totsuka , Koichiro Ishibashi , Hiroyuki Mizuno , Osamu Nishii , Kunio Uchiyama , Takanori Shimura , Asako Sekine , Yoichi Katsuki , Susumu Narita
发明人： Yonetaro Totsuka , Koichiro Ishibashi , Hiroyuki Mizuno , Osamu Nishii , Kunio Uchiyama , Takanori Shimura , Asako Sekine , Yoichi Katsuki , Susumu Narita
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32 , G06F11/30 , H02J1/00
CPC分类号： G06F1/3296 , G06F1/3203 , Y02D10/172 , Y02D50/20
摘要： The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.

7. 发明授权

US07475261B2 Substrate bias switching unit for a low power processor 有权
标题翻译：用于低功耗处理器的基板偏置开关单元
公开(公告)号：US07475261B2
公开(公告)日：2009-01-06
申请号：US10768136
申请日：2004-02-02
申请人： Yonetaro Totsuka , Koichiro Ishibashi , Hiroyuki Mizuno , Osamu Nishii , Kunio Uchiyama , Takanori Shimura , Asako Sekine , Yoichi Katsuki , Susumu Narita
发明人： Yonetaro Totsuka , Koichiro Ishibashi , Hiroyuki Mizuno , Osamu Nishii , Kunio Uchiyama , Takanori Shimura , Asako Sekine , Yoichi Katsuki , Susumu Narita
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： G06F1/3296 , G06F1/3203 , Y02D10/172 , Y02D50/20
摘要： The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.
摘要翻译：本发明的特征在于：处理器主电路，用于在处理器芯片上执行程序指令串; 衬底偏置切换单元，用于切换施加到处理器主电路的衬底的衬底偏压的电压; 以及操作模式控制单元，用于响应于执行处理器主电路中的待机模式的指令，控制所述衬底偏置切换单元，使得所述偏置切换到所述处理器主电路的电压待机模式，并且为了响应于来自外部的待机释放的中断来控制衬底偏置切换单元，使得偏置被切换到用于正常模式的电压，并且还用于释放在切换到其上的偏置电压已经稳定之后，处理器主电路的待机重新开始操作。

8. 发明授权

US06715090B1 Processor for controlling substrate biases in accordance to the operation modes of the processor 有权
标题翻译：用于根据处理器的操作模式控制衬底偏压的处理器
公开(公告)号：US06715090B1
公开(公告)日：2004-03-30
申请号：US09308488
申请日：1999-05-20
申请人： Yonetaro Totsuka , Koichiro Ishibashi , Hiroyuki Mizuno , Osamu Nishii , Kunio Uchiyama , Takanori Shimura , Asako Sekine , Yoichi Katsuki , Susumu Narita
发明人： Yonetaro Totsuka , Koichiro Ishibashi , Hiroyuki Mizuno , Osamu Nishii , Kunio Uchiyama , Takanori Shimura , Asako Sekine , Yoichi Katsuki , Susumu Narita
IPC分类号： G06F130
CPC分类号： G06F1/3296 , G06F1/3203 , Y02D10/172 , Y02D50/20
摘要： The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.
摘要翻译：本发明的特征在于：处理器主电路，用于在处理器芯片上执行程序指令串; 衬底偏置切换单元，用于切换施加到处理器主电路的衬底的衬底偏压的电压; 以及操作模式控制单元，用于响应于执行处理器主电路中的待机模式的指令，控制所述衬底偏置切换单元，使得所述偏置切换到所述处理器主电路的电压待机模式，并且为了响应于来自外部的待机释放的中断来控制衬底偏置切换单元，使得偏置被切换到用于正常模式的电压，并且还用于释放在切换到其上的偏置电压已经稳定之后，处理器主电路的待机重新开始操作。

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