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1. 发明申请

US20100005436A1 METHOD AND APPARATUS FOR CHARACTERIZING AN INTEGRATED CIRCUIT MANUFACTURING PROCESS 有权
标题翻译：用于表征集成电路制造工艺的方法和装置
公开(公告)号：US20100005436A1
公开(公告)日：2010-01-07
申请号：US12166781
申请日：2008-07-02
申请人： Mark Laird , Wayne Clark , Yiping Szu
发明人： Mark Laird , Wayne Clark , Yiping Szu
IPC分类号： G06F17/50
CPC分类号： H01L22/12 , H01L22/20
摘要： A system that characterizes an integrated circuit manufacturing process is presented. During operation, the system receives a layout which includes a plurality of test structures for semiconductor devices, wherein each test structure varies one or more design variables. The system then fabricates a plurality of wafers based on the layout, wherein each wafer in the plurality of wafers is fabricated using one of a plurality of process settings. Next, the system obtains performance characteristics for the plurality of test structures on the plurality of wafers. The system then generates a process model that is based on at least the effect that values for the one or more design variables and the plurality of process settings have on the performance characteristics of the plurality of test structures.
摘要翻译：介绍了一个表征集成电路制造过程的系统。在操作期间，系统接收包括用于半导体器件的多个测试结构的布局，其中每个测试结构改变一个或多个设计变量。然后，系统基于布局制造多个晶片，其中使用多个工艺设置中的一个来制造多个晶片中的每个晶片。接下来，系统获得多个晶片上的多个测试结构的性能特征。该系统然后基于至少基于一个或多个设计变量和多个处理设置的值对多个测试结构的性能特征的影响来生成过程模型。

2. 发明授权

US08091063B2 Method and apparatus for characterizing an integrated circuit manufacturing process 有权
标题翻译：用于表征集成电路制造过程的方法和装置
公开(公告)号：US08091063B2
公开(公告)日：2012-01-03
申请号：US12166781
申请日：2008-07-02
申请人： Mark Laird , Wayne Clark , Yiping Szu
发明人： Mark Laird , Wayne Clark , Yiping Szu
IPC分类号： G06F17/50
CPC分类号： H01L22/12 , H01L22/20
摘要： A system that characterizes an integrated circuit manufacturing process is presented. During operation, the system receives a layout which includes a plurality of test structures for semiconductor devices, wherein each test structure varies one or more design variables. The system then fabricates a plurality of wafers based on the layout, wherein each wafer in the plurality of wafers is fabricated using one of a plurality of process settings. Next, the system obtains performance characteristics for the plurality of test structures on the plurality of wafers. The system then generates a process model that is based on at least the effect that values for the one or more design variables and the plurality of process settings have on the performance characteristics of the plurality of test structures.
摘要翻译：介绍了一个表征集成电路制造过程的系统。在操作期间，系统接收包括用于半导体器件的多个测试结构的布局，其中每个测试结构改变一个或多个设计变量。然后，系统基于布局制造多个晶片，其中使用多个工艺设置中的一个来制造多个晶片中的每个晶片。接下来，系统获得多个晶片上的多个测试结构的性能特征。该系统然后基于至少基于一个或多个设计变量和多个处理设置的值对多个测试结构的性能特征的影响来生成过程模型。

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