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1. 发明授权

US06674130B2 High performance PD SOI tunneling-biased MOSFET 有权
标题翻译：高性能PD SOI隧道偏置MOSFET
公开(公告)号：US06674130B2
公开(公告)日：2004-01-06
申请号：US10316601
申请日：2002-12-11
申请人： Kuo-Nan Yang , Yi-Ling Chan , You-Lin Chu , Hou-Yu Chen , Fu-Liang Yang , Chenming Hu
发明人： Kuo-Nan Yang , Yi-Ling Chan , You-Lin Chu , Hou-Yu Chen , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L2362
CPC分类号： H01L29/4983 , H01L29/0895 , H01L29/1041 , H01L29/1083 , H01L29/4238 , H01L29/42384 , H01L29/4908 , H01L29/78612 , H01L2924/0002 , Y10S438/979 , H01L2924/00
摘要： A new type of partially-depleted SOI MOSFET is described in which a tunneling connection between the gate and the base is introduced. This is achieved by using a gate dielectric whose thickness is below its tunneling threshold. The gate pedestal is made somewhat longer than normal and a region near one end is implanted to be P+ (or N+ in a PMOS device). This allows holes (electrons for PMOS) to tunnel from gate to base. Since the hole current is self limiting, applied voltages greater than 0.7 volts may be used without incurring excessive leakage (as is the case with prior art DTMOS devices). A process for manufacturing the device is also described.
摘要翻译：描述了一种新型的部分耗尽的SOI MOSFET，其中引入了栅极和基极之间的隧道连接。这通过使用其厚度低于其隧道阈值的栅极电介质实现。栅极基座比正常长一些，一端附近的区域植入P +（或PMOS器件中的N +）。这允许空穴（PMOS的电子）从栅极到基极隧道。由于空穴电流是自限制的，所以可以使用大于0.7伏的施加电压，而不会引起过大的泄漏（如现有技术的DTMOS器件的情况）。还描述了用于制造该装置的方法。

2. 发明申请

US20070063261A1 Necked Finfet device 审中-公开
标题翻译：颈缩Finfet设备
公开(公告)号：US20070063261A1
公开(公告)日：2007-03-22
申请号：US11548772
申请日：2006-10-12
申请人： Haur-Ywh CHEN , Fang-Cheng CHEN , Yi-Ling CHAN , Kuo-Nan YANG , Fu-Liang YANG , Chenming HU
发明人： Haur-Ywh CHEN , Fang-Cheng CHEN , Yi-Ling CHAN , Kuo-Nan YANG , Fu-Liang YANG , Chenming HU
IPC分类号： H01L29/788 , H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/785 , H01L29/665 , H01L29/66795
摘要： A method of fabricating a double gate, FINFET device structure in a silicon on insulator layer, in which the channel region formed in the SOI layer is defined with a narrowed, or necked shape, and wherein a composite insulator spacer is formed on the sides of the device structure, has been developed. A FINFET device structure shape is formed in an SOI layer via anisotropic RIE procedures, followed by a growth of a silicon dioxide gate insulator layer on the sides of the FINFET device structure shape. A gate structure is fabricated traversing the device structure and overlying the silicon dioxide gate insulator layer located on both sides of the narrowest portion of channel region. After formation of a source/drain region in wider, non-channel regions of the FINFET device structure shape, composite insulator spacers are formed on the sides of the FINFET shape and on the sides of the gate structure. Metal silicide is next formed on source/drain regions resulting in a FINFET device structure featuring a narrow channel region, and surrounded by composite insulator spacers located on the sides of the device structure.
摘要翻译：一种在绝缘体上硅层制造双栅极FINFET器件结构的方法，其中形成在SOI层中的沟道区域被限定为窄的或颈部形状，并且其中复合绝缘体隔离物形成在器件结构，已经开发。通过各向异性RIE工艺在SOI层中形成FINFET器件结构形状，随后在FINFET器件结构形状的侧面上生长二氧化硅栅极绝缘体层。制造横跨器件结构并覆盖位于沟道区域最窄部分两侧的二氧化硅栅极绝缘体层的栅极结构。在FINFET器件结构形状的较宽的非沟道区域中形成源极/漏极区域之后，在FINFET形状的侧面和栅极结构的侧面上形成复合绝缘体间隔物。金属硅化物接着形成在源极/漏极区域上，导致FINFET器件结构的特征是窄的沟道区域，并被位于器件结构侧面的复合绝缘体隔离物围绕。

3. 发明授权

US07122412B2 Method of fabricating a necked FINFET device 有权
标题翻译：制造颈缩FINFET器件的方法
公开(公告)号：US07122412B2
公开(公告)日：2006-10-17
申请号：US10835789
申请日：2004-04-30
申请人： Haur-Ywh Chen , Fang-Cheng Chen , Yi-Ling Chan , Kuo-Nan Yang , Fu-Liang Yang , Chenming Hu
发明人： Haur-Ywh Chen , Fang-Cheng Chen , Yi-Ling Chan , Kuo-Nan Yang , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L29/785 , H01L29/665 , H01L29/66795
摘要： A method of fabricating a double gate, FINFET device structure in a silicon on insulator layer, in which the channel region formed in the SOI layer is defined with a narrowed, or necked shape, and wherein a composite insulator spacer is formed on the sides of the device structure, has been developed. A FINFET device structure shape is formed in an SOI layer via anisotropic RIE procedures, followed by a growth of a silicon dioxide gate insulator layer on the sides of the FINFET device structure shape. A gate structure is fabricated traversing the device structure and overlying the silicon dioxide gate insulator layer located on both sides of the narrowest portion of channel region. After formation of a source/drain region in wider, non-channel regions of the FINFET device structure shape, composite insulator spacers are formed on the sides of the FINFET shape and on the sides of the gate structure. Metal silicide is next formed on source/drain regions resulting in a FINFET device structure featuring a narrow channel region, and surrounded by composite insulator spacers located on the sides of the device structure.
摘要翻译：一种在绝缘体上硅层制造双栅极FINFET器件结构的方法，其中形成在SOI层中的沟道区域被限定为窄的或颈部形状，并且其中复合绝缘体隔离物形成在器件结构，已经开发。通过各向异性RIE工艺在SOI层中形成FINFET器件结构形状，随后在FINFET器件结构形状的侧面上生长二氧化硅栅极绝缘体层。制造横跨器件结构并覆盖位于沟道区域最窄部分两侧的二氧化硅栅极绝缘体层的栅极结构。在FINFET器件结构形状的较宽的非沟道区域中形成源极/漏极区域之后，在FINFET形状的侧面和栅极结构的侧面上形成复合绝缘体间隔物。金属硅化物接着形成在源极/漏极区域上，导致FINFET器件结构的特征是窄的沟道区域，并被位于器件结构侧面的复合绝缘体隔离物围绕。

4. 发明授权

US06800516B2 Electrostatic discharge device protection structure 有权
公开(公告)号：US06800516B2
公开(公告)日：2004-10-05
申请号：US10348387
申请日：2003-01-21
申请人： Yi-Ling Chan , Fu-Liang Yang , Yi Ming Sheu
发明人： Yi-Ling Chan , Fu-Liang Yang , Yi Ming Sheu
IPC分类号： H01L21336
CPC分类号： H01L21/26506 , H01L29/0847 , H01L29/7835
摘要： The problem of gate oxide damage as a result of electrostatic discharges has been overcome by including within the drain of the ESD protection device a region having very high defect density. Its depth within the drain is such that no action occurs when applied voltages are low. However, when a high voltage is applied, the depletion layer grows wide enough to touch this region thereby allowing substantial current flow into the substrate which results in lowering the voltage to a safe level. The high defect density region is formed through ion implantation of relatively heavy ions such as germanium. This is done after completion of the normal manufacturing process including SALICIDATION, no significant heating of the device after that being permitted.

5. 发明授权

US06784071B2 Bonded SOI wafer with <100> device layer and <110> substrate for performance improvement 有权
标题翻译：具有<100>器件层和<110>衬底的粘合SOI晶片，以提高性能
公开(公告)号：US06784071B2
公开(公告)日：2004-08-31
申请号：US10355872
申请日：2003-01-31
申请人： Haur-Ywh Chen , Yi-Ling Chan , Kuo-Nan Yang , Fu-Liang Yang , Chenming Hu
发明人： Haur-Ywh Chen , Yi-Ling Chan , Kuo-Nan Yang , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L2130
CPC分类号： H01L21/76251 , Y10S438/977
摘要： A new silicon structure is provided. Under a first embodiment of the invention, a first silicon substrate having a crystallographic orientation is bonded to the surface of a second silicon substrate having a crystallographic orientation, the wafer alignment notch of the first and the second silicon substrates are aligned with each other. Under a first embodiment of the invention, a first silicon substrate having a crystallographic orientation is bonded to the surface of a second silicon substrate having a crystallographic orientation, the wafer alignment notch of the first and the second silicon substrates are not aligned with each other.
摘要翻译：提供了新的硅结构。在本发明的第一实施例中，具有<100>晶体取向的第一硅衬底被结合到具有<110>晶体取向的第二硅衬底的表面上，第一和第二硅衬底的晶片对准凹槽是彼此对齐。在本发明的第一实施例中，具有<100>晶体取向的第一硅衬底被结合到具有<110>晶体取向的第二硅衬底的表面上，第一和第二硅衬底的晶片对准凹槽是不对齐。

6. 发明申请

US20050253193A1 Method of fabricating a necked finfet device 有权
标题翻译：制造颈缩鳍片装置的方法
公开(公告)号：US20050253193A1
公开(公告)日：2005-11-17
申请号：US10835789
申请日：2004-04-30
申请人： Haur-Ywh Chen , Fang-Cheng Chen , Yi-Ling Chan , Kuo-Nan Yang , Fu-Liang Yang , Chenming Hu
发明人： Haur-Ywh Chen , Fang-Cheng Chen , Yi-Ling Chan , Kuo-Nan Yang , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/336 , H01L29/786
CPC分类号： H01L29/785 , H01L29/665 , H01L29/66795
摘要： A method of fabricating a double gate, FINFET device structure in a silicon on insulator layer, in which the channel region formed in the SOI layer is defined with a narrowed, or necked shape, and wherein a composite insulator spacer is formed on the sides of the device structure, has been developed. A FINFET device structure shape is formed in an SOI layer via anisotropic RIE procedures, followed by a growth of a silicon dioxide gate insulator layer on the sides of the FINFET device structure shape. A gate structure is fabricated traversing the device structure and overlying the silicon dioxide gate insulator layer located on both sides of the narrowest portion of channel region. After formation of a source/drain region in wider, non-channel regions of the FINFET device structure shape, composite insulator spacers are formed on the sides of the FINFET shape and on the sides of the gate structure. Metal silicide is next formed on source/drain regions resulting in a FINFET device structure featuring a narrow channel region, and surrounded by composite insulator spacers located on the sides of the device structure.
摘要翻译：一种在绝缘体上硅层制造双栅极FINFET器件结构的方法，其中形成在SOI层中的沟道区域被限定为窄的或颈部形状，并且其中复合绝缘体隔离物形成在器件结构，已经开发。通过各向异性RIE工艺在SOI层中形成FINFET器件结构形状，随后在FINFET器件结构形状的侧面上生长二氧化硅栅极绝缘体层。制造横跨器件结构并覆盖位于沟道区域最窄部分两侧的二氧化硅栅极绝缘体层的栅极结构。在FINFET器件结构形状的较宽的非沟道区域中形成源极/漏极区域之后，在FINFET形状的侧面和栅极结构的侧面上形成复合绝缘体间隔物。金属硅化物接着形成在源极/漏极区域上，导致FINFET器件结构的特征是窄的沟道区域，并被位于器件结构侧面的复合绝缘体隔离物围绕。

7. 发明授权

US06673683B1 Damascene gate electrode method for fabricating field effect transistor (FET) device with ion implanted lightly doped extension regions 有权
标题翻译：用于制造具有离子注入的轻掺杂延伸区的场效应晶体管（FET）器件的镶嵌栅极电极方法
公开(公告)号：US06673683B1
公开(公告)日：2004-01-06
申请号：US10291029
申请日：2002-11-07
申请人： Yi-Ming Sheu , Yi-Ling Chan , Da-Wen Lin , Wan-Yih Lien , Carlos H. Diaz
发明人： Yi-Ming Sheu , Yi-Ling Chan , Da-Wen Lin , Wan-Yih Lien , Carlos H. Diaz
IPC分类号： H01L21336
CPC分类号： H01L29/66553 , H01L29/66545 , H01L29/6659
摘要： A method for forming a field effect transistor device within a semiconductor product employs a patterned dummy layer first as an ion implantation mask layer when forming a pair of source/drain regions, and then as a mandrel layer for forming a pair of patterned sacrificial layers which define an aperture of linewidth and location corresponding to the patterned dummy layer. A pair of sacrificial spacer layers and a gate electrode are then formed self-aligned within the aperture. The pair of patterned sacrificial layers and the pair of sacrificial spacer layers are then stripped and the gate electrode is employed as a mask for ion implanting forming a pair of lightly doped extension regions partially overlapping the pair of source/drain regions within the semiconductor substrate.
摘要翻译：在半导体产品中形成场效应晶体管器件的方法当形成一对源极/漏极区域时首先使用图案化虚拟层作为离子注入掩模层，然后作为用于形成一对图案化牺牲层的心轴层，限定对应于图案化虚拟层的线宽和位置的孔径。然后在孔内自对准地形成一对牺牲间隔层和栅电极。然后剥去一对图案化牺牲层和一对牺牲隔离层，并且使用栅电极作为用于离子注入的掩模，形成与半导体衬底内的一对源/漏区部分重叠的一对轻掺杂的延伸区。

8. 发明授权

US06518105B1 High performance PD SOI tunneling-biased MOSFET 有权
标题翻译：高性能PD SOI隧道偏置MOSFET
公开(公告)号：US06518105B1
公开(公告)日：2003-02-11
申请号：US10021702
申请日：2001-12-10
申请人： Kuo-Nan Yang , Yi-Ling Chan , You-Lin Chu , Hou-Yu Chen , Fu-Liang Yang , Chenming Hu
发明人： Kuo-Nan Yang , Yi-Ling Chan , You-Lin Chu , Hou-Yu Chen , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L2100
CPC分类号： H01L29/4983 , H01L29/0895 , H01L29/1041 , H01L29/1083 , H01L29/4238 , H01L29/42384 , H01L29/4908 , H01L29/78612 , H01L2924/0002 , Y10S438/979 , H01L2924/00
摘要： A new type of partially-depleted SOI MOSFET is described in which a tunneling connection between the gate and the base is introduced. This is achieved by using a gate dielectric whose thickness is below its tunneling threshold. The gate pedestal is made somewhat longer than normal and a region near one end is implanted to be P+ (or N+ in a PMOS device). This allows holes (electrons for PMOS) to tunnel from gate to base. Since the hole current is self limiting, applied voltages greater than 0.7 volts may be used without incurring excessive leakage (as is the case with prior art DTMOS devices). A process for manufacturing the device is also described.
摘要翻译：描述了一种新型的部分耗尽的SOI MOSFET，其中引入了栅极和基极之间的隧道连接。这通过使用其厚度低于其隧道阈值的栅极电介质实现。栅极基座比正常长一些，一端附近的区域植入P +（或PMOS器件中的N +）。这允许空穴（PMOS的电子）从栅极到基极隧道。由于空穴电流是自限制的，所以可以使用大于0.7伏的施加电压，而不会引起过大的泄漏（如现有技术的DTMOS器件的情况）。还描述了用于制造该装置的方法。

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