专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5646881A Semiconductor memory cell with increased refresh time 失效
标题翻译：半导体存储单元具有增加的刷新时间
公开(公告)号：US5646881A
公开(公告)日：1997-07-08
申请号：US588242
申请日：1996-01-18
申请人： Yi Hwan Park , Hyun Soo Shin , Yong-Bok Lee
发明人： Yi Hwan Park , Hyun Soo Shin , Yong-Bok Lee
IPC分类号： G11C11/404 , G11C11/403 , G11C11/406 , G11C11/407 , G11C11/4096 , G11C11/24
CPC分类号： G11C11/4096 , G11C11/406
摘要： In a DRAM cell, as a word line signal is applied to a gate of a MOS transistor, the MOS transistor writes the voltage applied to bit lines BL and BL into a capacitor. When a high level data is written, a voltage of the bit line BL or BL is increased to be higher than a power supply voltage, so as to permit reading of the data in a stable condition. When a capacitance value of the cell is the same as that of the conventional art, a refresh time of the present semiconductor memory, e.g., DRAM memory, is lengthened over that of the conventional art, whereas when the refresh time is the same as that of the conventional art, the capacitance value used in the present semiconductor memory can be reduced from that of the conventional art.
摘要翻译：在DRAM单元中，当MOS晶体管的栅极被施加字线信号时，MOS晶体管将施加到位线BL和+ E，ovs BL + EE的电压写入电容器。当写入高电平数据时，位线BL或+ E，ovs BL + EE的电压增加到高于电源电压，以便允许在稳定状态下读取数据。当单元的电容值与常规技术的电容值相同时，本发明半导体存储器（例如DRAM存储器）的刷新时间比常规技术的刷新时间延长，而当刷新时间与现有技术相同时在现有的半导体存储器中使用的电容值可以比传统技术中减少。

2. 发明授权

US5896323A Data output control circuit for semiconductor memory device 失效
标题翻译：半导体存储器件的数据输出控制电路
公开(公告)号：US5896323A
公开(公告)日：1999-04-20
申请号：US900340
申请日：1997-07-25
申请人： Yi Hwan Park , Hyun Soo Shin
发明人： Yi Hwan Park , Hyun Soo Shin
IPC分类号： G11C11/41 , G11C7/10 , G11C11/407 , G11C11/409 , G11C11/413 , G11C16/04
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/106
摘要： A data output control circuit for a semiconductor memory device sequentially transmits input data via a main amplifier controlled by an address transition detecting signal, a multiplex/latch unit, a data output buffer and an output operator. The data output control circuit prevents false data output, which also improves data processing speed by using a control signal. The data output control circuit includes an output control unit that converts an address transition detecting signal into a kill signal. The kill signal is applied to the data output buffer to cause the output operator to generate a zero level signal based on the address transition detecting signal. The data output control circuit enables the output operator to generate a zero level signal by applying the kill signal to the data output buffer when the transition of an address signal is detected. Accordingly, an interval for a data reversal or a full swing is prevented to enhance data processing speed and reduce current consumption.
摘要翻译：用于半导体存储器件的数据输出控制电路通过由地址转换检测信号控制的主放大器，多路复用/锁存单元，数据输出缓冲器和输出运算器顺序发送输入数据。数据输出控制电路防止伪数据输出，这也通过使用控制信号来提高数据处理速度。数据输出控制电路包括将地址转换检测信号转换为停止信号的输出控制单元。杀死信号被施加到数据输出缓冲器，以使得输出操作者基于地址转换检测信号产生零电平信号。当检测到地址信号的转换时，数据输出控制电路使得输出操作者能够通过将数据输出缓冲器应用到数据输出缓冲器来产生零电平信号。因此，防止数据反转或全摆动的间隔以提高数据处理速度并减少电流消耗。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式