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1. 发明授权

US09478502B2 Device identification assignment and total device number detection 有权
标题翻译：设备识别分配和设备编号检测
公开(公告)号：US09478502B2
公开(公告)日：2016-10-25
申请号：US13559235
申请日：2012-07-26
申请人： Yasuo Satoh
发明人： Yasuo Satoh
IPC分类号： H01L23/544 , G11C5/04 , G11C8/12 , G11C5/02 , G11C7/20 , G11C16/20 , H01L25/065 , G11C29/44
CPC分类号： H01L23/544 , G11C5/025 , G11C5/04 , G11C8/12 , G11C16/20 , G11C2029/4402 , H01L25/0657 , H01L2223/5444 , H01L2223/54473 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541
摘要： Various embodiments comprise apparatuses to assign a respective one of a sequence of unique device identification (ID) values to each die in a stacked device. In an embodiment, each die may include a respective assignment device to operate on an input and generate, as an output, the respective one of the sequence of the unique device ID values. Each die may also include a respective evaluation device to detect a total number of dice in the stack. Additional apparatuses and methods are described.
摘要翻译：各种实施例包括为堆叠设备中的每个管芯分配唯一设备标识（ID）值序列中的相应一个的装置。在一个实施例中，每个管芯可以包括相应的分配装置，以对输入进行操作，并且产生唯一装置ID值序列中相应的一个作为输出。每个管芯还可以包括用于检测堆叠中的管芯总数的相应的评估装置。描述附加的装置和方法。

2. 发明授权

US07940103B2 Duty cycle correction systems and methods 有权
标题翻译：占空比校正系统和方法
公开(公告)号：US07940103B2
公开(公告)日：2011-05-10
申请号：US12400495
申请日：2009-03-09
申请人： Yasuo Satoh , Eric Booth
发明人： Yasuo Satoh , Eric Booth
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03L7/0805 , H03L7/0812 , H03L7/087
摘要： Duty cycle correction systems and methods of adjusting duty cycles are provided. One such duty cycle correction system includes a duty cycle adjustor and a variable delay line coupled to the output of the duty cycle adjustor. First and second phase detectors have first inputs coupled to the output of the duty cycle adjustor through an inverter and second inputs coupled to the output of the variable delay line. The phase detectors cause the delay line to align rising or falling edges of signals at the output of the delay line with rising or falling edges, respectively, of signals at the output of the inverter. The controller simultaneously causes the duty cycle adjustor to adjust the duty cycle of the output clock signal until the rising and falling edges of signals at the output of the delay line are aligned with rising and falling edges, respectively, of signals at the output of the inverter.
摘要翻译：提供了占空比校正系统和调整占空比的方法。一个这样的占空比校正系统包括一个占空比调节器和一个与占空比调节器输出端耦合的可变延迟线。第一和第二相位检测器具有通过反相器耦合到占空比调节器的输出的第一输入端和耦合到可变延迟线的输出的第二输入端。相位检测器使延迟线在延迟线的输出端分别与反相器输出端的信号的上升沿或下降沿对齐信号的上升沿或下降沿。控制器同时使占空比调节器调整输出时钟信号的占空比，直到延迟线输出端的信号的上升沿和下降沿分别与输出端的信号的上升沿和下降沿对齐逆变器。

3. 发明授权

US07511644B2 Variable resistance logic 有权
标题翻译：可变电阻逻辑
公开(公告)号：US07511644B2
公开(公告)日：2009-03-31
申请号：US11780963
申请日：2007-07-20
申请人： Yasuo Satoh
发明人： Yasuo Satoh
IPC分类号： H03M7/20
CPC分类号： G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084
摘要： A system comprising a control logic that generates a code having n digits, a translation logic coupled to the control logic that translates the code to a new code having greater than n digits, and a variable resistance logic coupled to the translation logic and comprising greater than n semiconductor devices. A resistance associated with the variable resistance logic depends on activation statuses of the semiconductor devices. The translation logic adjusts at least some of the semiconductor devices in accordance with the new code.
摘要翻译：一种系统，包括产生具有n位的代码的控制逻辑，耦合到所述控制逻辑的转换逻辑，所述控制逻辑将所述代码转换为具有大于n位的新代码，以及耦合到所述翻译逻辑的可变电阻逻辑，并且包括大于 n半导体器件。与可变电阻逻辑相关联的电阻取决于半导体器件的激活状态。翻译逻辑根据新的代码来调整至少一些半导体器件。

4. 发明申请

US20090021404A1 VARIABLE RESISTANCE LOGIC 有权
标题翻译：可变电阻逻辑
公开(公告)号：US20090021404A1
公开(公告)日：2009-01-22
申请号：US11780963
申请日：2007-07-20
申请人： YASUO SATOH
发明人： YASUO SATOH
IPC分类号： H03M7/00 , H01C10/00
CPC分类号： G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084
摘要： A system comprising a control logic that generates a code having n digits, a translation logic coupled to the control logic that translates the code to a new code having greater than n digits, and a variable resistance logic coupled to the translation logic and comprising greater than n semiconductor devices. A resistance associated with the variable resistance logic depends on activation statuses of the semiconductor devices. The translation logic adjusts at least some of the semiconductor devices in accordance with the new code.
摘要翻译：一种系统，包括产生具有n位的代码的控制逻辑，耦合到所述控制逻辑的转换逻辑，所述控制逻辑将所述代码转换为具有大于n位的新代码，以及耦合到所述翻译逻辑的可变电阻逻辑，并且包括大于 n半导体器件。与可变电阻逻辑相关联的电阻取决于半导体器件的激活状态。翻译逻辑根据新的代码来调整至少一些半导体器件。

5. 发明申请

US20060135712A1 Ethylened polymer and molded object obtained therefrom 有权
标题翻译：乙烯化聚合物和由其得到的成型体
公开(公告)号：US20060135712A1
公开(公告)日：2006-06-22
申请号：US10539038
申请日：2003-12-15
申请人： Yasuo Satoh , Mamoru Takahashi , Hideki Bando , Yoshiho Sonobe , Yasushi Nakayama
发明人： Yasuo Satoh , Mamoru Takahashi , Hideki Bando , Yoshiho Sonobe , Yasushi Nakayama
IPC分类号： C08F4/44
CPC分类号： C08F10/00 , C08F4/65916 , C08F4/65927 , C08F4/65912
摘要： An ethylene-based polymer which is an ethylene/C4 to C10 α-olefin copolymer and satisfies the following requirements [k1] to [k3]: [k1] melt flow rate (MFR) under a loading of 2.16 kg at 190° C. is in the range of 1.0 to 50 g/10 minutes; [k2] LNR defined as a scale of neck-in upon film molding is in the range of 0.6 to 1.4; and [k3] take-up speed at break [DS (m/min)] at 160° C. and melt flow rate (MFR) satisfy the following relationship (Eq-1): 12×MFR0.577≦DS≦165×MFR0.577 (Eq-1), and a thermoplastic resin composition containing the ethylene-based polymer, provide a molded product, preferably a film, excellent in moldability and mechanical strength. The ethylene-based polymer can be efficiently obtained by polymerization in the presence of an olefin polymerization catalyst formed from a solid carrier, (A) a solid transition metal catalyst component obtained by contacting (a) a compound of a transition metal of the group 4 in the periodic table, containing at least one ligand having a cyclopentadienyl skeleton, (b) an organoaluminum oxy compound, (c) a multifunctional organic halide, and if necessary (d) an organoaluminum compound, and if necessary (B) organoaluminum compound.
摘要翻译：乙烯基聚合物是乙烯/ C 4〜C 10α-烯烃共聚物，满足以下要求[k1]〜[k3]：[k1]在190℃下2.16kg负载下的熔体流动速率（MFR）在1.0〜50g / 10分钟的范围内; [k2]在膜成型时定义为颈缩尺度的LNR在0.6至1.4的范围内; 和[k3]在160℃下的卷取速度[DS（m / min）]，熔体流动速率（MFR）满足以下关系式（Eq-1）：12xMFR 0.577 < （式-1），含有乙烯类聚合物的热塑性树脂组合物提供成型性和机械强度优异的成型品，优选为薄膜。通过在由固体载体形成的烯烃聚合催化剂的存在下聚合可有效获得乙烯类聚合物，（A）通过使（a）第4族过渡金属的化合物在周期表中，含有至少一种具有环戊二烯基骨架的配体，（b）有机铝氧化合物，（c）多官能有机卤化物，以及必要时（d）有机铝化合物，以及必要时（B）有机铝化合物。

6. 发明授权

US5838890A Household information system data processor changing an inital image 失效
标题翻译：家庭信息系统数据处理器改变初始图像
公开(公告)号：US5838890A
公开(公告)日：1998-11-17
申请号：US774587
申请日：1996-12-24
申请人： Yoichi Aoki , Yasuo Satoh , Chiaki Ito , Seizi Kakizawa , Shinichi Konya , Haruhiko Mio , Makoto Wanishi , Takeo Asawa
发明人： Yoichi Aoki , Yasuo Satoh , Chiaki Ito , Seizi Kakizawa , Shinichi Konya , Haruhiko Mio , Makoto Wanishi , Takeo Asawa
IPC分类号： G06F9/06 , G06F3/048 , G06F3/14 , G06F3/153 , G06F9/445 , G06T11/80 , G06T13/00 , G06T13/80 , G06F3/00
CPC分类号： G06F9/4401
摘要： A data processor such as a household information system which is realized by an image display with which the initial image of the system changes every time the system is started, and the displayed object moves interactively, employing a small memory. When the power source of the processor is turned on, the initial image display processing unit is started. In the initial image display processing unit, the screen display update processing unit changes the image on the display unit every after a predetermined period of time based upon the state of the images that have been stored in advance in the state storage unit. Moreover, any input from the input unit is detected by the input detect unit. Then, the image state select processing unit selects the state of a new image that corresponds to the input and stores it in the state storage unit.
摘要翻译：一种数据处理器，例如家庭信息系统，其通过每次系统启动时系统的初始图像改变的图像显示器实现，并且所显示的对象以交互方式移动，采用小的存储器。当打开处理器的电源时，启动初始图像显示处理单元。在初始图像显示处理单元中，屏幕显示更新处理单元基于预先存储在状态存储单元中的图像的状态，在预定时间段之后改变显示单元上的图像。此外，输入单元的任何输入都由输入检测单元检测。然后，图像状态选择处理单元选择对应于输入的新图像的状态并将其存储在状态存储单元中。

7. 发明授权

US5375069A Wiring routes in a plurality of wiring layers 失效
标题翻译：在多个布线层中布线
公开(公告)号：US5375069A
公开(公告)日：1994-12-20
申请号：US184753
申请日：1994-01-21
申请人： Yasuo Satoh , Takuji Itoh
发明人： Yasuo Satoh , Takuji Itoh
IPC分类号： H01L21/82 , G06F17/50 , H01L27/118 , G06F15/60
CPC分类号： G06F17/5077
摘要： A wiring processing method for determining a wiring route for connecting terminals includes a step of dividing a wirable region into a plurality of rectangular regions in a virtual region corresponding to a chip, a step of searching a rectangular region for connecting the terminals to be wired by tracing mutually crossings rectangular regions, and a step of determining a detailed wiring route inside the searched rectangular region. Since the search is conducted by use of the rectangular region as a unit, high speed search can be made.
摘要翻译：用于确定用于连接端子的布线路径的布线处理方法包括将可引导区域划分成与芯片对应的虚拟区域中的多个矩形区域的步骤，搜索用于连接待布线端子的矩形区域的步骤跟踪交叉矩形区域，以及确定搜索到的矩形区域内的详细布线路线的步骤。由于通过使用矩形区域作为单元进行搜索，因此可以进行高速搜索。

8. 发明申请

US20140027771A1 DEVICE IDENTIFICATION ASSIGNMENT AND TOTAL DEVICE NUMBER DETECTION 有权
标题翻译：设备识别分配和总设备号码检测
公开(公告)号：US20140027771A1
公开(公告)日：2014-01-30
申请号：US13559235
申请日：2012-07-26
申请人： Yasuo Satoh
发明人： Yasuo Satoh
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , G11C5/025 , G11C5/04 , G11C8/12 , G11C16/20 , G11C2029/4402 , H01L25/0657 , H01L2223/5444 , H01L2223/54473 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541
摘要： Various embodiments comprise apparatuses to assign a respective one of a sequence of unique device identification (ID) values to each die in a stacked device. In an embodiment, each die may include a respective assignment device to operate on an input and generate, as an output, the respective one of the sequence of the unique device ID values. Each die may also include a respective evaluation device to detect a total number of dice in the stack. Additional apparatuses and methods are described.
摘要翻译：各种实施例包括为堆叠设备中的每个管芯分配唯一设备标识（ID）值序列中的相应一个的装置。在一个实施例中，每个管芯可以包括相应的分配装置，以对输入进行操作，并且产生唯一装置ID值序列中相应的一个作为输出。每个管芯还可以包括用于检测堆叠中的管芯总数的相应的评估装置。描述附加的装置和方法。

9. 发明申请

US20130342254A1 APPARATUSES AND METHODS FOR ADJUSTING A MINIMUM FORWARD PATH DELAY OF A SIGNAL PATH 有权
标题翻译：调整信号路径最小前进路径延迟的装置和方法
公开(公告)号：US20130342254A1
公开(公告)日：2013-12-26
申请号：US13531341
申请日：2012-06-22
申请人： Kallol Mazumder , Jongtae Kwak , Tsugio Takahashi , Yasuo Satoh
发明人： Kallol Mazumder , Jongtae Kwak , Tsugio Takahashi , Yasuo Satoh
IPC分类号： H03H11/26
CPC分类号： H03H11/26
摘要： Apparatuses and methods related to adjusting a minimum forward path delay of a signal path are disclosed. One such signal path includes a signal path having a minimum forward path delay, wherein the signal path is configured to adjust the minimum forward path delay based at least in part on a selected latency and a propagation delay of the minimum forward path delay. An example method includes reducing a forward path delay of a command path by at least one clock cycle of a clock signal to provide a command according to a selected latency responsive to a count value representative of a minimum forward path delay of the command path being greater than a maximum count value for the selected latency.
摘要翻译：公开了与调整信号路径的最小前向路径延迟相关的装置和方法。一个这样的信号路径包括具有最小正向路径延迟的信号路径，其中信号路径被配置为至少部分地基于所选等待时间和最小前向路径延迟的传播延迟来调整最小前向路径延迟。一个示例性方法包括：通过时钟信号的至少一个时钟周期来减少命令路径的前向路径延迟，以根据表示命令路径的最小前向路径延迟的计数值的选定延迟来提供命令更大比所选延迟的最大计数值。

10. 发明申请

US20100225372A1 DUTY CYCLE CORRECTION SYSTEMS AND METHODS 有权
标题翻译：占空比校正系统和方法
公开(公告)号：US20100225372A1
公开(公告)日：2010-09-09
申请号：US12400495
申请日：2009-03-09
申请人： Yasuo Satoh , Eric Booth
发明人： Yasuo Satoh , Eric Booth
IPC分类号： H03K5/04
CPC分类号： H03K5/1565 , H03L7/0805 , H03L7/0812 , H03L7/087
摘要： Duty cycle correction systems and methods of adjusting duty cycles are provided. One such duty cycle correction system includes a duty cycle adjustor and a variable delay line coupled to the output of the duty cycle adjustor. First and second phase detectors have first inputs coupled to the output of the duty cycle adjustor through an inverter and second inputs coupled to the output of the variable delay line. The phase detectors cause the delay line to align rising or falling edges of signals at the output of the delay line with rising or falling edges, respectively, of signals at the output of the inverter. The controller simultaneously causes the duty cycle adjustor to adjust the duty cycle of the output clock signal until the rising and falling edges of signals at the output of the delay line are aligned with rising and falling edges, respectively, of signals at the output of the inverter.
摘要翻译：提供了占空比校正系统和调整占空比的方法。一个这样的占空比校正系统包括一个占空比调节器和一个与占空比调节器输出端耦合的可变延迟线。第一和第二相位检测器具有通过反相器耦合到占空比调节器的输出的第一输入端和耦合到可变延迟线的输出的第二输入端。相位检测器使延迟线分别在延迟线的输出端分别与反相器输出端的信号的上升沿或下降沿对齐信号的上升沿或下降沿。控制器同时使占空比调节器调整输出时钟信号的占空比，直到延迟线输出端的信号的上升沿和下降沿分别与输出端的信号的上升沿和下降沿对齐逆变器。

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