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    • 2. 发明授权
    • Computer system with interface and method
    • 具有接口和方法的计算机系统
    • US06182181B2
    • 2001-01-30
    • US08999178
    • 1997-12-29
    • Ezra BaruchYaron GoldDan M. Bruck
    • Ezra BaruchYaron GoldDan M. Bruck
    • G06F1300
    • G06F13/1642
    • An interface (101) in a computer system has an port (150) which is coupled to a memory via a first bi-directional data path (104) and coupled to a peripheral device via a communication path (106). The interface (101) has a controller (170) with an enable portion (176) and a pointer register (160). The pointer register (160) provides a movable pointer (165) to memory entries of data queues. The enable portion (176) continuously receives control signals from the memory (130) and sends enable signals to a port (150). A queue of memory entries is transmitted through the first path (104), the port (150) and the second path (106) or vice versa as long as control signals stored in the queue itself allow a transmission.
    • 计算机系统中的接口(101)具有经由第一双向数据路径(104)耦合到存储器并且经由通信路径(106)耦合到外围设备的端口(150)。 接口(101)具有具有使能部分(176)和指针寄存器(160)的控制器(170)。 指针寄存器(160)为数据队列的存储器条目提供可移动指针(165)。 使能部分(176)连续接收来自存储器(130)的控制信号,并向端口(150)发送使能信号。 只要存储在队列本身中的控制信号允许传输,则通过第一路径(104),端口(150)和第二路径(106)或反之亦然地传送存储器条目的队列。
    • 4. 发明授权
    • Computer system with trigger controlled interface and method
    • 具有触发控制接口和方法的计算机系统
    • US6125413A
    • 2000-09-26
    • US999274
    • 1997-12-29
    • Ezra BaruchYaron GoldDan M. Bruck
    • Ezra BaruchYaron GoldDan M. Bruck
    • G06F13/38G06F13/00
    • G06F13/385
    • An interface (101) in a computer system has an port (150) which is coupled to a memory via a first bidirectional data path (104) and coupled to a peripheral device via a communication path (106). The interface (101) has a controller (170) with a trigger buffer (175) and a pointer register (160). The pointer register (160) provides a movable pointer (165) to memory entries of data queues. The trigger buffer (175) continuously receives and accumulates trigger signals (1 2 3) and sends start signals to the pointer register (165). A queue is transmitted through the first path (104), the port (150) and the second path (106) or vice versa when a first trigger (e.g., (1) signal arrives. The trigger buffer (175) receives further trigger signals (e.g., (2) and accumulates them in a trigger buffer (175) before it sends start signals (e.g., ) for further transmissions. Optionally, interface 101 provides start signals after prioritizing trigger signals.
    • 计算机系统中的接口(101)具有经由第一双向数据路径(104)耦合到存储器并且经由通信路径(106)耦合到外围设备的端口(150)。 接口(101)具有带触发缓冲器(175)和指针寄存器(160)的控制器(170)。 指针寄存器(160)为数据队列的存储器条目提供可移动指针(165)。 触发缓冲器(175)连续地接收和累加触发信号(+ E,crc 1 + EE + E,crc 2 + EE + E,crc 3 + EE),并将起始信号+ Z + Z + Z发送到指针寄存器 165)。 当第一触发(例如,(+ E,crc 1 + EE))信号到达时,队列通过第一路径(104),端口(150)和第二路径(106)传输,反之亦然。触发缓冲器 175)接收另外的触发信号(例如,(+ E,crc 2 + EE),并在它们发送启动信号(例如,+ Z)之前将其累加在触发缓冲器(175)中,以供进一步传输。 优先触发信号。