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1. 发明授权

US08658499B2 Three dimensional NAND device and method of charge trap layer separation and floating gate formation in the NAND device 有权
标题翻译： NAND器件中的三维NAND器件和电荷陷阱层分离和浮栅形成方法
公开(公告)号：US08658499B2
公开(公告)日：2014-02-25
申请号：US13544328
申请日：2012-07-09
申请人： Raghuveer S. Makala , Johann Alsmeier , Yao-Sheng Lee
发明人： Raghuveer S. Makala , Johann Alsmeier , Yao-Sheng Lee
IPC分类号： H01L27/115 , H01L21/8246
CPC分类号： H01L27/11582 , H01L21/28273 , H01L21/28282 , H01L21/7682 , H01L27/11529 , H01L27/11551 , H01L27/11556 , H01L27/11573 , H01L27/11578 , H01L29/7889 , H01L29/7926
摘要： A monolithic three dimensional NAND string includes a vertical semiconductor channel and a plurality of control gate electrodes in different device levels. The string also includes a blocking dielectric layer, a charge storage region and a tunnel dielectric. A first control gate electrode is separated from a second control gate electrode by an air gap located between the major surfaces of the first and second control gate electrodes and/or the charge storage region includes silicide nanoparticles embedded in a charge storage dielectric.
摘要翻译：单片三维NAND串包括垂直半导体通道和不同器件级别的多个控制栅电极。该串还包括阻挡介电层，电荷存储区和隧道电介质。第一控制栅电极通过位于第一和第二控制栅电极的主表面之间的气隙与第二控制栅极分离，和/或电荷存储区包括嵌入电荷存储电介质中的硅化物纳米颗粒。

2. 发明授权

US08614126B1 Method of making a three-dimensional memory array with etch stop 有权
标题翻译：制造具有蚀刻停止的三维存储阵列的方法
公开(公告)号：US08614126B1
公开(公告)日：2013-12-24
申请号：US13586413
申请日：2012-08-15
申请人： Yao-Sheng Lee , Johann Alsmeier
发明人： Yao-Sheng Lee , Johann Alsmeier
IPC分类号： H01L21/8238
CPC分类号： H01L27/11551 , H01L21/764 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11578 , H01L27/11582 , H01L29/7889 , H01L29/7926
摘要： A three dimensional memory device including a substrate and a semiconductor channel. At least one end portion of the semiconductor channel extends substantially perpendicular to a major surface of the substrate. The device also includes at least one charge storage region located adjacent to semiconductor channel and a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate. The plurality of control gate electrodes include at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level. The device also includes an etch stop layer located between the substrate and the plurality of control gate electrodes.
摘要翻译：一种包括衬底和半导体沟道的三维存储器件。半导体通道的至少一个端部基本上垂直于衬底的主表面延伸。该器件还包括位于半导体通道附近的至少一个电荷存储区域以及具有基本上平行于衬底的主表面延伸的条带形状的多个控制栅极电极。多个控制栅电极至少包括位于第一器件级的第一控制栅电极和位于位于衬底的主表面上方且低于第一器件电平的第二器件电平的第二控制栅电极。该器件还包括位于衬底和多个控制栅电极之间的蚀刻停止层。

3. 发明授权

US08330208B2 Ultrahigh density monolithic three dimensional vertical NAND string memory device and method of making thereof 有权
标题翻译：超高密度单片三维垂直NAND串存储器件及其制造方法
公开(公告)号：US08330208B2
公开(公告)日：2012-12-11
申请号：US13451009
申请日：2012-04-19
申请人： Johann Alsmeier , Vinod Robert Purayath , Henry Chien , George Matamis , Yao-Sheng Lee , James Kai , Yuan Zhang
发明人： Johann Alsmeier , Vinod Robert Purayath , Henry Chien , George Matamis , Yao-Sheng Lee , James Kai , Yuan Zhang
IPC分类号： H01L29/788
CPC分类号： H01L29/788 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/7889 , H01L29/7926
摘要： Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.
摘要翻译：单片三维NAND串包括半导体通道，半导体通道的至少一个端部基本上垂直于基板的主表面延伸，多个控制栅电极具有基本上平行于基板的主表面延伸的带状衬底，所述阻挡电介质包括多个阻挡电介质段，多个离散电荷存储段和位于所述多个离散电荷存储段和所述半导体通道中的每一个之间的隧道电介质。

4. 发明申请

US20050040136A1 Method for making memory elements 审中-公开
标题翻译：制作记忆元素的方法
公开(公告)号：US20050040136A1
公开(公告)日：2005-02-24
申请号：US10895277
申请日：2004-07-20
申请人： Yao-Sheng Lee , Mike DeVre
发明人： Yao-Sheng Lee , Mike DeVre
IPC分类号： H01L45/00 , B44C1/22
CPC分类号： H01L45/06 , H01L45/144 , H01L45/1675
摘要： The present invention provides an improved method for forming a memory element having a chalcogenide layer such as Ge2Sb2Te5. A substrate having a dielectric etch stop layer, a chalcogenide layer, an anti-reflective layer and a mask layer is placed in a vacuum chamber having a high density plasma source. At least one chlorine containing gas, such as a mixture of BCl3 and Cl2, is introduced into the vacuum chamber for etching the chalcogenide layer and the anti-reflective layer to the dielectric etch stop layer. The etch process is discontinued based on an endpoint detection system. Upon completion of the etch process, the substrate is removed from the vacuum chamber and the mask layer is stripped from the substrate.
摘要翻译：本发明提供了一种用于形成具有诸如Ge 2 Sb 2 Te 5的硫族化物层的存储元件的改进方法。将具有电介质蚀刻停止层，硫族化物层，抗反射层和掩模层的衬底放置在具有高密度等离子体源的真空室中。将至少一种含氯气体，例如BCl 3和Cl 2的混合物引入真空室中，用于将硫族化物层和抗反射层蚀刻到电介质蚀刻停止层。基于端点检测系统停止蚀刻工艺。在完成蚀刻工艺后，将基板从真空室中取出，掩模层从基板上剥离。

5. 发明申请

US20150076584A1 HIGH ASPECT RATIO MEMORY HOLE CHANNEL CONTACT FORMATION 有权
标题翻译：高比例记忆孔通道接触形成
公开(公告)号：US20150076584A1
公开(公告)日：2015-03-19
申请号：US14225176
申请日：2014-03-25
申请人： Jayavel Pachamuthu , Johann Alsmeier , Raghuveer S. Makala , Yao-Sheng Lee
发明人： Jayavel Pachamuthu , Johann Alsmeier , Raghuveer S. Makala , Yao-Sheng Lee
IPC分类号： H01L29/788 , H01L29/792 , H01L21/28
CPC分类号： H01L21/28282 , H01L21/28273 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： A memory device and a method of fabricating a memory device that includes forming a protrusion over a substrate, an etch stop layer over the protrusion, and a stack of alternating material layers over the etch stop layer. The method further includes etching the stack to the etch stop layer to form a memory opening having a first width dimension proximate to the etch stop layer, etching the etch stop layer to provide a void area between the protrusion and a bottom of the memory opening, where the void area has a second width dimension that is larger than the first width dimension, forming a memory film over a sidewall of the memory opening and within the void area over the top surface of the protrusion, etching the memory film to expose the protrusion, and forming a semiconductor channel in the memory opening that is electrically coupled to the protrusion.
摘要翻译：一种存储器件和一种制造存储器件的方法，所述存储器件包括在衬底上形成突起，在所述突起上方形成蚀刻停止层，以及在所述蚀刻停止层上方的交替材料层堆叠。所述方法还包括将所述叠层蚀刻到所述蚀刻停止层以形成具有靠近所述蚀刻停止层的第一宽度尺寸的存储器开口，蚀刻所述蚀刻停止层以在所述突起与所述存储器开口的底部之间提供空隙区域，其中所述空隙区域具有大于所述第一宽度尺寸的第二宽度尺寸，在所述存储器开口的侧壁上并且在所述突起的顶表面上方的所述空隙区域内形成记忆膜，蚀刻所述存储膜以暴露所述突起并且在与所述突起电耦合的所述存储器开口中形成半导体通道。

6. 发明申请

US20140008714A1 Three Dimensional NAND Device and Method of Charge Trap Layer Separation and Floating Gate Formation in the NAND Device 有权
标题翻译： NAND器件中的三维NAND器件和电荷陷阱层分离和浮栅形成的方法
公开(公告)号：US20140008714A1
公开(公告)日：2014-01-09
申请号：US13544328
申请日：2012-07-09
申请人： Raghuveer S. Makala , Johann Alsmeier , Yao-Sheng Lee
发明人： Raghuveer S. Makala , Johann Alsmeier , Yao-Sheng Lee
IPC分类号： H01L27/088 , H01L21/8239
CPC分类号： H01L27/11582 , H01L21/28273 , H01L21/28282 , H01L21/7682 , H01L27/11529 , H01L27/11551 , H01L27/11556 , H01L27/11573 , H01L27/11578 , H01L29/7889 , H01L29/7926
摘要： A monolithic three dimensional NAND string includes a vertical semiconductor channel and a plurality of control gate electrodes in different device levels. The string also includes a blocking dielectric layer, a charge storage region and a tunnel dielectric. A first control gate electrode is separated from a second control gate electrode by an air gap located between the major surfaces of the first and second control gate electrodes and/or the charge storage region includes silicide nanoparticles embedded in a charge storage dielectric.
摘要翻译：单片三维NAND串包括垂直半导体通道和不同器件级别的多个控制栅电极。该串还包括阻挡介电层，电荷存储区和隧道电介质。第一控制栅电极通过位于第一和第二控制栅电极的主表面之间的气隙与第二控制栅极分离，和/或电荷存储区包括嵌入电荷存储电介质中的硅化物纳米颗粒。

7. 发明申请

US20130313627A1 Multi-Level Contact to a 3D Memory Array and Method of Making 有权
标题翻译：与3D内存阵列的多层接触及其制作方法
公开(公告)号：US20130313627A1
公开(公告)日：2013-11-28
申请号：US13478483
申请日：2012-05-23
申请人： Yao-Sheng Lee , Zhen Chen , Syo Fukata
发明人： Yao-Sheng Lee , Zhen Chen , Syo Fukata
IPC分类号： H01L21/768 , H01L29/792 , H01L23/48
CPC分类号： H01L27/11578 , H01L21/76816 , H01L21/76829 , H01L23/481 , H01L27/10802 , H01L27/11 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11548 , H01L27/11556 , H01L27/11565 , H01L27/11568 , H01L27/1157 , H01L27/11575 , H01L27/11582 , H01L29/66 , H01L29/7926 , H01L2924/0002 , H01L2924/00
摘要： A method of making multi-level contacts. The method includes providing an in-process multilevel device including at least one device region and at least one contact region. The contact region includes a plurality of electrically conductive layers configured in a step pattern. The method also includes forming a conformal etch stop layer over the plurality of electrically conductive layers, forming a first electrically insulating layer over the etch stop layer, forming a conformal sacrificial layer over the first electrically insulating layer and forming a second electrically insulating layer over the sacrificial layer. The method also includes etching a plurality of contact openings through the etch stop layer, the first electrically insulating layer, the sacrificial layer and the second electrically insulating layer in the contact region to the plurality of electrically conductive layers.
摘要翻译：制作多层次联系的方法。该方法包括提供包括至少一个设备区域和至少一个接触区域的进程内多电平设备。接触区域包括以台阶图案配置的多个导电层。该方法还包括在多个导电层上形成共形蚀刻停止层，在蚀刻停止层上形成第一电绝缘层，在第一电绝缘层上形成共形牺牲层，并形成第二电绝缘层牺牲层。该方法还包括通过蚀刻停止层，接触区域中的第一电绝缘层，牺牲层和第二电绝缘层蚀刻到多个导电层的多个接触开口。

8. 发明申请

US20120001252A1 ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF 有权
公开(公告)号：US20120001252A1
公开(公告)日：2012-01-05
申请号：US12827947
申请日：2010-06-30
申请人： Johann Alsmeier , Vinod Robert Purayath , Henry Chien , George Matamis , Yao-Sheng Lee , James Kai , Yuan Zhang
发明人： Johann Alsmeier , Vinod Robert Purayath , Henry Chien , George Matamis , Yao-Sheng Lee , James Kai , Yuan Zhang
IPC分类号： H01L27/115 , H01L21/8246 , H01L21/8247 , H01L29/788 , H01L21/336
CPC分类号： H01L29/788 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/7889 , H01L29/7926
摘要： Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.

9. 发明授权

US08828884B2 Multi-level contact to a 3D memory array and method of making 有权
标题翻译：与3D内存阵列的多层次接触和制作方法
公开(公告)号：US08828884B2
公开(公告)日：2014-09-09
申请号：US13478483
申请日：2012-05-23
申请人： Yao-Sheng Lee , Zhen Chen , Syo Fukata
发明人： Yao-Sheng Lee , Zhen Chen , Syo Fukata
IPC分类号： H01L21/467
CPC分类号： H01L27/11578 , H01L21/76816 , H01L21/76829 , H01L23/481 , H01L27/10802 , H01L27/11 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11548 , H01L27/11556 , H01L27/11565 , H01L27/11568 , H01L27/1157 , H01L27/11575 , H01L27/11582 , H01L29/66 , H01L29/7926 , H01L2924/0002 , H01L2924/00
摘要： A method of making multi-level contacts. The method includes providing an in-process multilevel device including at least one device region and at least one contact region. The contact region includes a plurality of electrically conductive layers configured in a step pattern. The method also includes forming a conformal etch stop layer over the plurality of electrically conductive layers, forming a first electrically insulating layer over the etch stop layer, forming a conformal sacrificial layer over the first electrically insulating layer and forming a second electrically insulating layer over the sacrificial layer. The method also includes etching a plurality of contact openings through the etch stop layer, the first electrically insulating layer, the sacrificial layer and the second electrically insulating layer in the contact region to the plurality of electrically conductive layers.
摘要翻译：制作多层次联系的方法。该方法包括提供包括至少一个设备区域和至少一个接触区域的进程内多电平设备。接触区域包括以台阶图案配置的多个导电层。该方法还包括在多个导电层上形成共形蚀刻停止层，在蚀刻停止层上形成第一电绝缘层，在第一电绝缘层上形成共形牺牲层，并形成第二电绝缘层牺牲层。该方法还包括通过蚀刻停止层，接触区域中的第一电绝缘层，牺牲层和第二电绝缘层蚀刻到多个导电层的多个接触开口。

10. 发明申请

US20140138760A1 THREE DIMENSIONAL NAND DEVICE AND METHOD OF CHARGE TRAP LAYER SEPARATION AND FLOATING GATE FORMATION IN THE NAND DEVICE 有权
标题翻译：三维NAND器件和NAND器件中充电陷阱层分离和浮动栅格形成的方法
公开(公告)号：US20140138760A1
公开(公告)日：2014-05-22
申请号：US14166162
申请日：2014-01-28
申请人： Raghuveer S. Makala , Johann Alsmeier , Yao-Sheng Lee
发明人： Raghuveer S. Makala , Johann Alsmeier , Yao-Sheng Lee
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L21/28273 , H01L21/28282 , H01L21/7682 , H01L27/11529 , H01L27/11551 , H01L27/11556 , H01L27/11573 , H01L27/11578 , H01L29/7889 , H01L29/7926
摘要： A monolithic three dimensional NAND string includes a vertical semiconductor channel and a plurality of control gate electrodes in different device levels. The string also includes a blocking dielectric layer, a charge storage region and a tunnel dielectric. A first control gate electrode is separated from a second control gate electrode by an air gap located between the major surfaces of the first and second control gate electrodes and/or the charge storage region includes silicide nanoparticles embedded in a charge storage dielectric.
摘要翻译：单片三维NAND串包括垂直半导体通道和不同器件级别的多个控制栅电极。该串还包括阻挡介电层，电荷存储区和隧道电介质。第一控制栅电极通过位于第一和第二控制栅电极的主表面之间的气隙与第二控制栅极分离，和/或电荷存储区包括嵌入电荷存储电介质中的硅化物纳米颗粒。

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