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1. 发明申请

US20120248431A1 TRANSISTOR ARRAY SUBSTRATE 审中-公开
标题翻译：晶体管阵列基板
公开(公告)号：US20120248431A1
公开(公告)日：2012-10-04
申请号：US13183838
申请日：2011-07-15
申请人： Ya-Huei HUANG , Kuan-Yu Chen , Ying-Hui Chen , Te-Yu Chen
发明人： Ya-Huei HUANG , Kuan-Yu Chen , Ying-Hui Chen , Te-Yu Chen
IPC分类号： H01L29/786
CPC分类号： H01L27/1225
摘要： A transistor array substrate includes a substrate, a plurality of scan lines, a plurality of data lines and a plurality of pixel units. The scan lines and the data lines are all disposed on the substrate. Each pixel unit includes a transistor and a pixel electrode. The transistor is electrically connected to the pixel electrodes, the scan lines and the data lines. Each transistor includes a gate, a drain, a source, a metal-oxide-semiconductor layer and a channel protective layer. A channel gap exists between the drain and the source. The metal-oxide-semiconductor layer has a pair of side edges opposite to each other and the side edges are located at two ends of the channel gap. The channel protective layer covers the metal-oxide-semiconductor layer in the channel gap and protrudes from the side edges of the metal-oxide-semiconductor layer.
摘要翻译：晶体管阵列基板包括基板，多条扫描线，多条数据线和多个像素单元。扫描线和数据线都设置在基板上。每个像素单元包括晶体管和像素电极。晶体管电连接到像素电极，扫描线和数据线。每个晶体管包括栅极，漏极，源极，金属氧化物半导体层和沟道保护层。漏极和源极之间存在沟道间隙。金属氧化物半导体层具有彼此相对的一对侧边缘，并且侧边缘位于沟道间隙的两端。沟道保护层覆盖沟道间隙中的金属氧化物半导体层，并从金属氧化物半导体层的侧边缘突出。

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