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1. 发明授权

US08421509B1 Charge pump circuit with low clock feed-through 有权
标题翻译：具有低时钟馈通电荷泵电路
公开(公告)号：US08421509B1
公开(公告)日：2013-04-16
申请号：US13280366
申请日：2011-10-25
申请人： Chien-Liang Chen , Ya-Nan Mou , Yuan-Hui Chen , Yu-Jen Chang
发明人： Chien-Liang Chen , Ya-Nan Mou , Yuan-Hui Chen , Yu-Jen Chang
IPC分类号： H03L7/06
CPC分类号： H03L7/0893
摘要： A charge pump circuit includes a first comparator, a PMOS tuner, a first current mirror, a first NMOS transistor, a first PMOS switch, an NMOS tuner, a second current mirror, a first PMOS transistor and a first NMOS switch. The first PMOS switch is coupled between the PMOS tuner and a first output PMOS transistor of the first current mirror, thus the parasitic capacitor formed between the gate and the drain of the first PMOS switch, the parasitic capacitor formed between the gate and the source of the first output PMOS transistor, and the parasitic capacitor formed between the gate and the drain of the first output PMOS transistor are equivalently coupled in series, lowering the capacitance between the PMOS tuner and the charge pump output, and reducing the clock feed through and the charge injection effect in the charge pump circuit.
摘要翻译：电荷泵电路包括第一比较器，PMOS调谐器，第一电流镜，第一NMOS晶体管，第一PMOS开关，NMOS调谐器，第二电流镜，第一PMOS晶体管和第一NMOS开关。第一PMOS开关耦合在PMOS调谐器和第一电流镜的第一输出PMOS晶体管之间，因此形成在第一PMOS开关的栅极和漏极之间的寄生电容器，形成在栅极和源极之间的寄生电容器第一输出PMOS晶体管和形成在第一输出PMOS晶体管的栅极和漏极之间的寄生电容器被等效地串联耦合，降低了PMOS调谐器和电荷泵输出之间的电容，并且减少了时钟馈通和电荷泵电路中的电荷注入效应。

2. 发明授权

US5973510A I/O interface for multilevel circuits 失效
标题翻译：用于多电平电路的I / O接口
公开(公告)号：US5973510A
公开(公告)日：1999-10-26
申请号：US059685
申请日：1998-04-14
申请人： Ya-Nan Mou
发明人： Ya-Nan Mou
IPC分类号： H03K19/0185 , H03K19/175
CPC分类号： H03K19/018521
摘要： The input and output interface in the present invention can includes following components. A first circuit and a second circuit are placed. Means for switching a coupling between the two circuits is used. Grounding means is employed for setting the first terminal to a ground connection. Triggering means is used for triggering the grounding means and the switching means. The method for interfacing input and output between a first circuit and a second circuit includes the steps as follows. At first, an output disable signal of the first circuit is detected. Then a first terminal is isolated from a second terminal. The first terminal is an input and output terminal of the first circuit and the second terminal is an input and output terminal of the second circuit. Next, the first terminal is grounded. The first terminal is then floated. Finally, the first terminal and the second terminal is coupled for the first circuit to receive an output signal from the second circuit.
摘要翻译：本发明的输入输出接口可包括以下部件。放置第一电路和第二电路。使用用于切换两个电路之间的耦合的装置。接地装置用于将第一端子设置为接地连接。触发装置用于触发接地装置和开关装置。用于在第一电路和第二电路之间连接输入和输出的方法包括以下步骤。首先，检测第一电路的输出禁止信号。然后，第一终端与第二终端隔离。第一端子是第一电路的输入和输出端子，第二端子是第二电路的输入和输出端子。接下来，第一端子接地。然后第一个终端浮动。最后，第一端子和第二端子被耦合用于第一电路以接收来自第二电路的输出信号。

3. 发明授权

US07274085B1 Capacitor structure 有权
标题翻译：电容结构
公开(公告)号：US07274085B1
公开(公告)日：2007-09-25
申请号：US11308162
申请日：2006-03-09
申请人： Tsun-Lai Hsu , Ya-Nan Mou , Yu-Yee Liow
发明人： Tsun-Lai Hsu , Ya-Nan Mou , Yu-Yee Liow
IPC分类号： H01L29/00
CPC分类号： H01L28/87 , H01G4/005 , H01G4/30 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A capacitor structure has a plurality of stacked conductive patterns, and each conductive pattern has a closed conductive ring, a plurality of major conductive bars arranged in parallel and electrically to the closed conductive ring, and a plurality of minor conductive bars arranged alternately with the major conductive bars and not electrically connected to the closed conductive ring. The major conductive bars and the minor conductive bars of an odd layer conductive pattern are respectively corresponding to the minor conductive bars and the major conductive bars of an even layer conductive pattern.
摘要翻译：电容器结构具有多个堆叠的导电图案，并且每个导电图案具有封闭的导电环，与闭合导电环并联布置的多个主要导电棒，以及与主要交替布置的多个次要导电棒导电棒并且不电连接到闭合导电环。奇数层导电图案的主导电棒和次导电棒分别对应于均匀导电图案的次导电棒和主导电棒。

4. 发明申请

US20070210416A1 CAPACITOR STRUCTURE 有权
标题翻译：电容结构
公开(公告)号：US20070210416A1
公开(公告)日：2007-09-13
申请号：US11308162
申请日：2006-03-09
申请人： Tsun-Lai Hsu , Ya-Nan Mou , Yu-Yee Liow
发明人： Tsun-Lai Hsu , Ya-Nan Mou , Yu-Yee Liow
IPC分类号： H01L29/00
CPC分类号： H01L28/87 , H01G4/005 , H01G4/30 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A capacitor structure has a plurality of stacked conductive patterns, and each conductive pattern has a closed conductive ring, a plurality of major conductive bars arranged in parallel and electrically to the closed conductive ring, and a plurality of minor conductive bars arranged alternately with the major conductive bars and not electrically connected to the closed conductive ring. The major conductive bars and the minor conductive bars of an odd layer conductive pattern are respectively corresponding to the minor conductive bars and the major conductive bars of an even layer conductive pattern.
摘要翻译：电容器结构具有多个堆叠的导电图案，并且每个导电图案具有封闭的导电环，与闭合导电环并联布置的多个主要导电棒，以及与主要交替布置的多个次要导电棒导电棒并且不电连接到闭合导电环。奇数层导电图案的主导电棒和次导电棒分别对应于均匀导电图案的次导电棒和主导电棒。

5. 发明授权

US5940873A Address-translation method and system for translating effective addresses into physical addressee in computers 失效
标题翻译：地址转换方法和系统，用于将有效地址转换为计算机中的物理地址
公开(公告)号：US5940873A
公开(公告)日：1999-08-17
申请号：US927067
申请日：1997-09-10
申请人： Ya-Nan Mou
发明人： Ya-Nan Mou
IPC分类号： G06F12/10
CPC分类号： G06F12/1036
摘要： An address-translation method is provided for efficiently translating effective addresses into physical addresses in X-86 based computers. In this method and system, when an effective address is generated, a segment base is then generated from a segment-descriptor cache memory in response to a selector address from the microcode. The segment base is added to the effective address to thereby obtain a linear address and a carry from the addition of the low-order portions of the segment base and the effective address. This carry is added to the high-order portion of the effective address to thereby obtain a comparison effective address. The comparison effective address and the segment base are then compared with a set of predetermined address values in a Translation Lookaside Buffer. If there is a match, a corresponding page base will be generated. The page base is then combined with the low-order portion of the linear address to thereby obtain the desired physical address. This address-translation method and system can speed up the access to the main memory since the address-translation and the linear address computation are proceeded in parallel, and also allow an increase in the hit ratio since the comparison process carried out in the Translation Lookaside Buffer involves the segment base from the segment-descriptor cache memory.
摘要翻译：提供了一种地址转换方法，用于将有效地址有效地转换为基于X-86的计算机中的物理地址。在该方法和系统中，当生成有效地址时，响应于来自微代码的选择器地址，从段描述符高速缓冲存储器生成段基。将段基加到有效地址，从而从段基的低阶部分和有效地址的相加获得线性地址和进位。该进位被添加到有效地址的高阶部分，从而获得比较有效地址。然后将比较有效地址和段基数与翻译后备缓冲器中的一组预定地址值进行比较。如果有匹配，将生成相应的页面基数。然后将页面基底与线性地址的低阶部分组合，从而获得所需的物理地址。由于地址转换和线性地址计算并行进行，这种地址转换方法和系统可以加速对主存储器的访问，并且还允许增加命中率，因为在翻译后备中执行比较处理缓冲区涉及段描述符缓存存储器中的段基。

6. 发明授权

US5705944A Method and device for detecting internal resistance voltage drop on a chip 失效
标题翻译：用于检测芯片内部电阻电压降的方法和装置
公开(公告)号：US5705944A
公开(公告)日：1998-01-06
申请号：US662690
申请日：1996-06-13
申请人： Ya-Nan Mou , Chien-Chung Pan
发明人： Ya-Nan Mou , Chien-Chung Pan
IPC分类号： G01R31/30 , G06F1/28 , H03K5/24
CPC分类号： G06F1/28 , G01R31/3004
摘要： The present invention provides a method and apparatus for detecting voltage drops on an IC chip. The device operates by using a reference voltage to detect the voltage range of a local voltage. A multiple number of reference voltages are used (or predetermined) between the reference voltage and the ground voltage. The voltage drop detecting device includes a multiple number of inverters having to the local voltage as its input. The inverters each have a trigger voltage corresponding to one of the reference positions. When the local voltage is smaller than the trigger voltage of the inverter, a low to high voltage switching is present at the output. A multiple number of positive-edge triggering devices, coupled to the reference voltage as one of its inputs, are each coupled to one of the inverters. A corresponding inverter presents a low to high switching to make the reference voltage present at the corresponding output terminal. The voltage range of the local voltage is detected at the output terminals.
摘要翻译：本发明提供一种用于检测IC芯片上的电压降的方法和装置。器件通过使用参考电压来工作，以检测局部电压的电压范围。在参考电压和接地电压之间使用多个参考电压（或预定的）。压降检测装置包括多个逆变器，其以本地电压作为其输入。逆变器各自具有对应于一个参考位置的触发电压。当本地电压小于逆变器的触发电压时，输出端存在低电平至高压开关。耦合到作为其输入之一的参考电压的多个正沿触发装置分别耦合到反相器中的一个。相应的反相器呈现低到高的开关，使参考电压存在于相应的输出端。在输出端检测本地电压的电压范围。

7. 发明申请

US20130099852A1 CHARGE PUMP CIRCUIT WITH LOW CLOCK FEED-THROUGH 有权
标题翻译：充电泵电路采用低时钟馈电
公开(公告)号：US20130099852A1
公开(公告)日：2013-04-25
申请号：US13280366
申请日：2011-10-25
申请人： Chien-Liang Chen , Ya-Nan Mou , Yuan-Hui Chen , Yu-Jen Chang
发明人： Chien-Liang Chen , Ya-Nan Mou , Yuan-Hui Chen , Yu-Jen Chang
IPC分类号： G05F3/02
CPC分类号： H03L7/0893
摘要： A charge pump circuit includes a first comparator, a PMOS tuner, a first current mirror, a first NMOS transistor, a first PMOS switch, an NMOS tuner, a second current mirror, a first PMOS transistor and a first NMOS switch. The first PMOS switch is coupled between the PMOS tuner and a first output PMOS transistor of the first current mirror, thus the parasitic capacitor formed between the gate and the drain of the first PMOS switch, the parasitic capacitor formed between the gate and the source of the first output PMOS transistor, and the parasitic capacitor formed between the gate and the drain of the first output PMOS transistor are equivalently coupled in series, lowering the capacitance between the PMOS tuner and the charge pump output, and reducing the clock feed through and the charge injection effect in the charge pump circuit.
摘要翻译：电荷泵电路包括第一比较器，PMOS调谐器，第一电流镜，第一NMOS晶体管，第一PMOS开关，NMOS调谐器，第二电流镜，第一PMOS晶体管和第一NMOS开关。第一PMOS开关耦合在PMOS调谐器和第一电流镜的第一输出PMOS晶体管之间，因此形成在第一PMOS开关的栅极和漏极之间的寄生电容器，形成在栅极和源极之间的寄生电容器第一输出PMOS晶体管和形成在第一输出PMOS晶体管的栅极和漏极之间的寄生电容器被等效地串联耦合，降低了PMOS调谐器和电荷泵输出之间的电容，并且减少了时钟馈通和电荷泵电路中的电荷注入效应。

8. 发明授权

US6028341A Latch up protection and yield improvement device for IC array 失效
标题翻译： IC阵列的保护和产量改进装置
公开(公告)号：US6028341A
公开(公告)日：2000-02-22
申请号：US36817
申请日：1998-03-09
申请人： Yu-Chin Tai , Ya-Nan Mou
发明人： Yu-Chin Tai , Ya-Nan Mou
IPC分类号： H01L27/02 , H01L27/112 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/112 , H01L27/0266
摘要： The integrated circuits array with latch up protection includes an active array and a guard array. The active array contains a plurality of integrated circuits devices having operational functions. The guard array abutting an outer peripheral portion of the active array contains a plurality of transistors for protecting the plurality of integrated circuits devices from latch up. In general, the active array can be functional circuits like a memory array or a read only memory (ROM) array. The plurality of transistors in the guard array can be formed simultaneously with transistors in the active array and have same structure with the transistors.
摘要翻译：具有闭锁保护的集成电路阵列包括有源阵列和保护阵列。有源阵列包含具有操作功能的多个集成电路器件。与有源阵列的外周部邻接的保护阵列包含多个晶体管，用于保护多个集成电路器件不被闩锁。通常，有源阵列可以是诸如存储器阵列或只读存储器（ROM）阵列之类的功能电路。保护阵列中的多个晶体管可以与有源阵列中的晶体管同时形成，并且与晶体管具有相同的结构。

9. 发明授权

US5646974A High speed apparatus for branch detection of a loop instruction 失效
标题翻译：用于循环指令的分支检测的高速设备
公开(公告)号：US5646974A
公开(公告)日：1997-07-08
申请号：US597386
申请日：1996-02-08
申请人： Wen-Yi Wu , Ya Nan Mou
发明人： Wen-Yi Wu , Ya Nan Mou
IPC分类号： G06F9/32 , G07C3/00
CPC分类号： G06F9/325
摘要： An apparatus for branch detecting a loop operation in a microprocessor. The apparatus includes a register, an ALU port, a predetector, an ALU, a flag generator and a branch detector. The register is provided for storing a loop information. Through the ALU port, the loop information is sent to the predetector and is predetected therein whenever the loop operation is about to proceed. A predetected result is then generated by the predetected and is sent to the branch detector to determine whether the loop operation has to be terminated. The ALU processes the loop information and updates new loop the register at the same time the predetection and detection tasks are performed by the predetector and the branch detector, respectively. The flag generator generates a flag which is independent of the detection and termination of the loop operation.
摘要翻译：一种用于分支检测微处理器中的循环操作的装置。该装置包括寄存器，ALU端口，预检测器，ALU，标志发生器和分支检测器。提供寄存器用于存储循环信息。通过ALU端口，循环信息被发送到预检测器，并且在循环操作即将进行时被预先检测。预先检测的结果然后由预先检测的产生，并被发送到分支检测器以确定是否必须终止循环操作。 ALU处理循环信息，并在预检测器和分支检测器分别执行预检测和检测任务的同时更新寄存器的循环。标志发生器产生独立于循环操作的检测和终止的标志。

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