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1. 发明授权

US07518243B2 Semiconductor device with multilayer interconnection structure 失效
标题翻译：具有多层互连结构的半导体器件
公开(公告)号：US07518243B2
公开(公告)日：2009-04-14
申请号：US11070165
申请日：2005-03-03
申请人： Yoshitake Tokumine
发明人： Yoshitake Tokumine
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5226 , H01L23/5222 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device with a multilayer interconnection structure comprises a semiconductor substrate, a plurality of metal wiring layers provided on the semiconductor device and electrically insulated from the upper and lower layers by an interlayer insulation film, and via holes penetrating through the interlayer insulation film and connecting the wirings of the first metal wiring layer and the second metal wiring layer positioned above the first metal wiring layer. And, potential of predetermined wiring of the first metal wiring layer is electrically floating from the semiconductor substrate, and a capacitance value between the wiring of the first metal wiring layer and the semiconductor substrate per one via provided on the predetermined wiring of the first metal wiring layer is a predetermined value or less. Thereby, in the semiconductor device with a multilayer interconnection structure comprising a plurality of metal wiring, a conduction failure caused by a high resistance layer which can be created at the time of via formation can be reduced.
摘要翻译：具有多层互连结构的半导体器件包括半导体衬底，设置在半导体器件上并通过层间绝缘膜与上层和下层电绝缘的多个金属布线层以及穿过层间绝缘膜和连接所述第一金属布线层和所述第二金属布线层的布线位于所述第一金属布线层的上方。并且，第一金属布线层的预定布线的电位从半导体衬底电浮置，并且设置在第一金属布线的预定布线上的每一个通孔中的第一金属布线层和半导体衬底的布线之间的电容值层是预定值以下。因此，在具有包含多个金属布线的多层互连结构的半导体器件中，可以减少由通孔形成时产生的高电阻层导致的导通故障。

2. 发明申请

US20110012268A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20110012268A1
公开(公告)日：2011-01-20
申请号：US12826737
申请日：2010-06-30
申请人： YASUAKI OZAKI , TOORU MASUTOMO , TAKAHIRO MATSUDA , YOSHITAKE TOKUMINE
发明人： YASUAKI OZAKI , TOORU MASUTOMO , TAKAHIRO MATSUDA , YOSHITAKE TOKUMINE
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/5226 , H01L21/76804 , H01L21/76805 , H01L23/53223 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： After opening a via hole, the bottom portion and the top portion are rounded by etching performed twice. As a result, resistance of the via hole can be reduced and its quality and life can be enhanced.
摘要翻译：打开通孔后，底部和顶部通过蚀刻进行两次倒圆。结果，可以减小通孔的电阻，并且可以提高其质量和寿命。

3. 发明申请

US20050194679A1 Semiconductor device with multilayer interconnection structure 失效
标题翻译：具有多层互连结构的半导体器件
公开(公告)号：US20050194679A1
公开(公告)日：2005-09-08
申请号：US11070165
申请日：2005-03-03
申请人： Yoshitake Tokumine
发明人： Yoshitake Tokumine
IPC分类号： H01L21/768 , H01L21/3205 , H01L21/4763 , H01L21/82 , H01L23/52
CPC分类号： H01L23/5226 , H01L23/5222 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device with a multilayer interconnection structure comprises a semiconductor substrate, a plurality of metal wiring layers provided on the semiconductor device and electrically insulated from the upper and lower layers by an interlayer insulation film, and via holes penetrating through the interlayer insulation film and connecting the wirings of the first metal wiring layer and the second metal wiring layer positioned above the first metal wiring layer. And, potential of predetermined wiring of the first metal wiring layer is electrically floating from the semiconductor substrate, and a capacitance value between the wiring of the first metal wiring layer and the semiconductor substrate per one via provided on the predetermined wiring of the first metal wiring layer is a predetermined value or less. Thereby, in the semiconductor device with a multilayer interconnection structure comprising a plurality of metal wiring, a conduction failure caused by a high resistance layer which can be created at the time of via formation can be reduced.
摘要翻译：具有多层互连结构的半导体器件包括半导体衬底，设置在半导体器件上并通过层间绝缘膜与上层和下层电绝缘的多个金属布线层以及穿过层间绝缘膜和连接所述第一金属布线层和所述第二金属布线层的布线位于所述第一金属布线层的上方。并且，第一金属布线层的预定布线的电位从半导体衬底电浮置，并且设置在第一金属布线的预定布线上的每一个通孔中的第一金属布线层和半导体衬底的布线之间的电容值层是预定值以下。因此，在具有包含多个金属布线的多层互连结构的半导体器件中，可以减少由通孔形成时产生的高电阻层导致的导通故障。

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