专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20140167995A1 ANALOG-TO-DIGITAL CONVERTER 审中-公开
标题翻译：模拟数字转换器
公开(公告)号：US20140167995A1
公开(公告)日：2014-06-19
申请号：US14111016
申请日：2012-04-11
申请人： Kei Tee Tiew , Kok Lim Chan , Minkyu Je , Xiaojun Yuan
发明人： Kei Tee Tiew , Kok Lim Chan , Minkyu Je , Xiaojun Yuan
IPC分类号： H03M1/00 , H03M3/00
CPC分类号： H03M1/002 , H03M3/30 , H03M3/422 , H03M3/444
摘要： According to embodiments of the present invention, an analog-to-digital converter is provided. The analog-to-digital converter includes an input configured to receive an input signal, a feed-forward path connected to the input configured to feed forward the input signal, a processing path including a loop filter, wherein the loop filter includes at least one local feedback path configured to feed back an output signal of the loop filter to an input of the loop filter, a first combiner configured to combine the input signal fed forward by the feed-forward path with an output of the processing path, a quantizer configured to generate an output signal of the converter, a feed-back path configured to feed back the output signal, and a second combiner wherein the processing path is connected to the second combiner and the second combiner is configured to combine the input signal with the fed back output signal of the converter and supply the result of the combination to the processing path.
摘要翻译：根据本发明的实施例，提供了一种模拟 - 数字转换器。模数转换器包括被配置为接收输入信号的输入端，连接到被配置为向前馈送输入信号的输入端的前馈路径，包括环路滤波器的处理路径，其中环路滤波器包括至少一个局部反馈路径，被配置为将环路滤波器的输出信号反馈到环路滤波器的输入;第一组合器，被配置为将由前馈路径馈送的输入信号与处理路径的输出组合;量化器配置以产生转换器的输出信号，被配置为反馈输出信号的反馈路径和第二组合器，其中处理路径连接到第二组合器，并且第二组合器被配置为将输入信号与馈送转换器的反向输出信号，并将组合的结果提供给处理路径。

2. 发明授权

US08367497B2 Method to reduce trench capacitor leakage for random access memory device 有权
公开(公告)号：US08367497B2
公开(公告)日：2013-02-05
申请号：US12680017
申请日：2007-10-31
申请人： Nace M. Rossi , Ranbir Singh , Xiaojun Yuan
发明人： Nace M. Rossi , Ranbir Singh , Xiaojun Yuan
IPC分类号： H01L21/8242 , H01L27/108
摘要： A method is provided that includes forming a trench isolation structure in a dynamic random memory region (DRAM) of a substrate and patterning an etch mask over the trench structure to expose a portion of the trench structure. A portion of the exposed trench structure is removed to form a gate trench that includes a first corner formed by the substrate and a second corner formed by the trench structure. The etch mask is removed and the first corner of the gate trench is rounded to form a rounded corner. This is followed by the formation of an oxide layer over a sidewall of the gate trench, the first rounded corner, and the semiconductor substrate adjacent the gate trench. The trench is filled with a gate material.

3. 发明申请

US20100065920A1 METHOD TO REDUCE COLLECTOR RESISTANCE OF A BIPOLAR TRANSISTOR AND INTEGRATION INTO A STANDARD CMOS FLOW 有权
标题翻译：降低双极晶体管的集电极电阻和集成到标准CMOS流量的方法
公开(公告)号：US20100065920A1
公开(公告)日：2010-03-18
申请号：US12523368
申请日：2007-02-14
申请人： Alan S. Chen , Mark Dyson , Nace M. Rossi , Ranbir Singh , Xiaojun Yuan
发明人： Alan S. Chen , Mark Dyson , Nace M. Rossi , Ranbir Singh , Xiaojun Yuan
IPC分类号： H01L27/06 , H01L21/8249
CPC分类号： H01L21/8249
摘要： The invention, in one aspect, provides a method for fabricating a semiconductor device. In one aspect, the method provides for a dual implantation of a tub of a bipolar transistor. The tub in bipolar region is implanted by implanting the tub through separate implant masks that are also used to implant tubs associated with MOS fabricate different voltage devices in a non-bipolar region during the fabrication of MOS transistors.
摘要翻译：本发明在一个方面提供一种用于制造半导体器件的方法。在一个方面，该方法提供双注入双极晶体管的桶。通过将单独的注入掩模注入到双极区域中，通过在MOS晶体管的制造期间也用于植入与在非双极区域中制造不同电压器件的MOS相关联的管道的桶。

4. 发明授权

US07456061B2 Method to reduce boron penetration in a SiGe bipolar device 有权
标题翻译：降低SiGe双极器件中硼渗透的方法
公开(公告)号：US07456061B2
公开(公告)日：2008-11-25
申请号：US11694021
申请日：2007-03-30
申请人： Alan S. Chen , Mark Dyson , Nace M. Rossi , Ranbir Singh , Xiaojun Yuan
发明人： Alan S. Chen , Mark Dyson , Nace M. Rossi , Ranbir Singh , Xiaojun Yuan
IPC分类号： H01L21/8238
CPC分类号： H01L29/7378 , H01L21/8249 , H01L27/0623 , H01L29/66242
摘要： The invention, in one aspect, provides a method of manufacturing a semiconductor device. This aspect includes forming gate electrodes in a non-bipolar transistor region of a semiconductor substrate, placing a polysilicon layer over the gate electrodes in the non-bipolar transistor region and over the semiconductor substrate within a bipolar transistor region. A protective layer is formed over the polysilicon layer. The protective layer has a weight percent of hydrogen that is less than about 9% and is selective to silicon germanium (SiGe), such that SiGe does not form on the protective layer. This aspect further includes forming emitters for bipolar transistors in the bipolar transistor region, including forming a SiGe layer under a portion of the polysilicon layer.
摘要翻译：本发明在一个方面提供一种制造半导体器件的方法。该方面包括在半导体衬底的非双极晶体管区域中形成栅电极，将多晶硅层放置在非双极晶体管区域中的栅电极之上，并在双极晶体管区域内的半导体衬底上。在多晶硅层上形成保护层。保护层具有小于约9％的氢的重量百分数，并且对硅锗（SiGe）是选择性的，使得SiGe不在保护层上形成。该方面还包括在双极晶体管区域中形成用于双极晶体管的发射极，包括在多晶硅层的一部分下形成SiGe层。

5. 发明申请

US20090050977A1 METHOD TO REDUCE BORON PENETRATION IN A SiGe BIPOLAR DEVICE 审中-公开
标题翻译：降低SiGe双极器件中硼孔渗透的方法
公开(公告)号：US20090050977A1
公开(公告)日：2009-02-26
申请号：US12256677
申请日：2008-10-23
申请人： Alan S. Chen , Mark Dyson , Nace M. Rossi , Ranbir Singh , Xiaojun Yuan
发明人： Alan S. Chen , Mark Dyson , Nace M. Rossi , Ranbir Singh , Xiaojun Yuan
IPC分类号： H01L27/06
CPC分类号： H01L29/7378 , H01L21/8249 , H01L27/0623 , H01L29/66242
摘要： The invention, in one aspect, provides a method of manufacturing a semiconductor device. This aspect includes forming gate electrodes in a non-bipolar transistor region of a semiconductor substrate, placing a polysilicon layer over the gate electrodes in the non-bipolar transistor region and over the semiconductor substrate within a bipolar transistor region. A protective layer is formed over the polysilicon layer. The protective layer has a weight percent of hydrogen that is less than about 9% and is selective to silicon germanium (SiGe), such that SiGe does not form on the protective layer. This aspect further includes forming emitters for bipolar transistors in the bipolar transistor region, including forming a SiGe layer under a portion of the polysilicon layer.
摘要翻译：本发明在一个方面提供一种制造半导体器件的方法。该方面包括在半导体衬底的非双极晶体管区域中形成栅电极，将多晶硅层放置在非双极晶体管区域中的栅电极之上，并在双极晶体管区域内的半导体衬底上。在多晶硅层上形成保护层。保护层具有小于约9％的氢的重量百分数，并且对硅锗（SiGe）是选择性的，使得SiGe不在保护层上形成。该方面还包括在双极晶体管区域中形成用于双极晶体管的发射极，包括在多晶硅层的一部分下形成SiGe层。

6. 发明授权

US08957732B2 Amplifier and transceiver including the amplifier 有权
标题翻译：放大器和收发器包括放大器
公开(公告)号：US08957732B2
公开(公告)日：2015-02-17
申请号：US13699867
申请日：2011-05-25
申请人： Hyouk Kyu Cha , Yuan Gao , Xiaojun Yuan
发明人： Hyouk Kyu Cha , Yuan Gao , Xiaojun Yuan
IPC分类号： H03F3/18 , H03F3/16 , H03F1/22 , H03F3/193 , H03F3/30 , H03F3/45
CPC分类号： H03F3/16 , H03F1/223 , H03F3/193 , H03F3/3028 , H03F3/45071 , H03F3/45179 , H03F2200/294 , H03F2200/408 , H03F2200/451 , H03F2200/492 , H03F2203/30078 , H03F2203/30081 , H03F2203/30111 , H03F2203/30114 , H03F2203/45646
摘要： An amplifier and a transceiver including the amplifier are provided. The amplifier includes an input terminal; a first transistor of a first conductivity and a second transistor of a second conductivity, each transistor comprising a source terminal, a gate terminal and a drain terminal respectively, the source terminal of the first transistor being coupled to the source terminal of the second transistor, and the gate terminal of the first transistor and the gate terminal of the second transistor being coupled to the input terminal; and an output terminal coupled to the drain terminal of the first transistor and the drain terminal of the second transistor.
摘要翻译：提供了放大器和包括放大器的收发器。放大器包括输入端子; 第一导电性的第一晶体管和第二导电性的第二晶体管，每个晶体管分别包括源极端子，栅极端子和漏极端子，所述第一晶体管的源极端子耦合到所述第二晶体管的源极端子，并且第一晶体管的栅极端子和第二晶体管的栅极端子耦合到输入端子; 以及耦合到第一晶体管的漏极端子和第二晶体管的漏极端子的输出端子。

7. 发明申请

US20130053711A1 Implantable Device for Detecting Variation in Fluid Flow Rate 审中-公开
标题翻译：用于检测流体流速变化的可植入装置
公开(公告)号：US20130053711A1
公开(公告)日：2013-02-28
申请号：US13503954
申请日：2010-09-27
申请人： Rama Krishna Kotlanka , Pradeep Basappa Khannur , Kok Lim Chan , Soo Yeng Benjamin Chua , Xiaojun Yuan , Minkyu Je , Vaidyanathan Kripesh , Daquan Yu , Pavel Neuzil , Lichun Shao , Woo Tae Park
发明人： Rama Krishna Kotlanka , Pradeep Basappa Khannur , Kok Lim Chan , Soo Yeng Benjamin Chua , Xiaojun Yuan , Minkyu Je , Vaidyanathan Kripesh , Daquan Yu , Pavel Neuzil , Lichun Shao , Woo Tae Park
IPC分类号： A61B5/0265
CPC分类号： A61B5/026 , A61B5/02007 , A61B5/02028 , A61B5/686 , A61B2560/0219 , G01F1/28 , G01F1/34 , G01F15/063
摘要： According to embodiments of the present invention, an implantable device for detecting variation in fluid flow rate is provided. The implantable device includes: a substrate having an active element arrangement; a sensor arrangement having a first portion that is mechanically secured and a second portion that is freely deflectable, the sensor arrangement in electrical communication with the active element arrangement, wherein the active element arrangement is configured to detect changes in deformation of the sensor arrangement and produce an output in response to the detected changes; and at least one inductive element mechanically coupled to the substrate and in electrical communication with the active element arrangement, wherein the inductive element is adapted to power the active element arrangement through inductive coupling to an excitation source, and wherein the inductive element is adapted to transmit the output associated with the detected changes in the sensor.
摘要翻译：根据本发明的实施例，提供了一种用于检测流体流量变化的可植入装置。该可植入装置包括：具有有源元件装置的衬底; 传感器装置，其具有机械固定的第一部分和可自由偏转的第二部分，所述传感器装置与所述有源元件装置电连通，其中所述有源元件布置被配置为检测所述传感器装置的变形的变化并产生响应于检测到的变化的输出; 以及至少一个电感元件，其机械耦合到所述衬底并与所述有源元件布置电连通，其中所述电感元件适于通过与激励源的感应耦合为所述有源元件布置供电，并且其中所述电感元件适于传输输出与传感器中检测到的变化相关联。

8. 发明授权

US07923340B2 Method to reduce collector resistance of a bipolar transistor and integration into a standard CMOS flow 有权
标题翻译：降低双极晶体管的集电极电阻并集成到标准CMOS流中的方法
公开(公告)号：US07923340B2
公开(公告)日：2011-04-12
申请号：US12523368
申请日：2007-02-14
申请人： Alan S. Chen , Mark Dyson , Nace M. Rossi , Ranbir Singh , Xiaojun Yuan
发明人： Alan S. Chen , Mark Dyson , Nace M. Rossi , Ranbir Singh , Xiaojun Yuan
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L21/8249
摘要： The invention, in one aspect, provides a method for fabricating a semiconductor device. In one aspect, the method provides for a dual implantation of a tub of a bipolar transistor. The tub in bipolar region is implanted by implanting the tub through separate implant masks that are also used to implant tubs associated with MOS fabricate different voltage devices in a non-bipolar region during the fabrication of MOS transistors.
摘要翻译：本发明在一个方面提供一种用于制造半导体器件的方法。在一个方面，该方法提供双注入双极晶体管的桶。通过将单独的注入掩模注入到双极区域中，通过在MOS晶体管的制造期间也用于植入与在非双极区域中制造不同电压器件的MOS相关联的管道的桶。

9. 发明申请

US20130169364A1 Amplifier and Transceiver Including the Amplifier 有权
标题翻译：放大器和收发器包括放大器
公开(公告)号：US20130169364A1
公开(公告)日：2013-07-04
申请号：US13699867
申请日：2011-05-25
申请人： Hyouk Kyu Cha , Yuan Gao , Xiaojun Yuan
发明人： Hyouk Kyu Cha , Yuan Gao , Xiaojun Yuan
IPC分类号： H03F3/16 , H03F3/45
CPC分类号： H03F3/16 , H03F1/223 , H03F3/193 , H03F3/3028 , H03F3/45071 , H03F3/45179 , H03F2200/294 , H03F2200/408 , H03F2200/451 , H03F2200/492 , H03F2203/30078 , H03F2203/30081 , H03F2203/30111 , H03F2203/30114 , H03F2203/45646
摘要： An amplifier and a transceiver including the amplifier are provided. The amplifier includes an input terminal; a first transistor of a first conductivity and a second transistor of a second conductivity, each transistor comprising a source terminal, a gate terminal and a drain terminal respectively, the source terminal of the first transistor being coupled to the source terminal of the second transistor, and the gate terminal of the first transistor and the gate terminal of the second transistor being coupled to the input terminal; and an output terminal coupled to the drain terminal of the first transistor and the drain terminal of the second transistor.
摘要翻译：提供了放大器和包括放大器的收发器。放大器包括输入端子; 第一导电性的第一晶体管和第二导电性的第二晶体管，每个晶体管分别包括源极端子，栅极端子和漏极端子，所述第一晶体管的源极端子耦合到所述第二晶体管的源极端子，并且第一晶体管的栅极端子和第二晶体管的栅极端子耦合到输入端子; 以及耦合到第一晶体管的漏极端子和第二晶体管的漏极端子的输出端子。

10. 发明申请

US20100264478A1 METHOD TO REDUCE TRENCH CAPACITOR LEAKAGE FOR RANDOM ACCESS MEMORY DEVICE 审中-公开
标题翻译：降低用于随机访问存储器件的TRENCH电容器泄漏的方法
公开(公告)号：US20100264478A1
公开(公告)日：2010-10-21
申请号：US12680017
申请日：2007-10-31
申请人： Nace M. Rossi , Ranbir Singh , Xiaojun Yuan
发明人： Nace M. Rossi , Ranbir Singh , Xiaojun Yuan
IPC分类号： H01L27/108 , H01L21/02 , H01L21/336 , H01L21/762
CPC分类号： H01L27/1087 , H01L21/76224 , H01L27/10829 , H01L27/10861
摘要： A method is provided that includes forming a trench isolation structure in a dynamic random memory region (DRAM) of a substrate and patterning an etch mask over the trench structure to expose a portion of the trench structure. A portion of the exposed trench structure is removed to form a gate trench that includes a first corner formed by the substrate and a second corner formed by the trench structure. The etch mask is removed and the first corner of the gate trench is rounded to form a rounded corner. This is followed by the formation of an oxide layer over a sidewall of the gate trench, the first rounded corner, and the semiconductor substrate adjacent the gate trench. The trench is filled with a gate material.
摘要翻译：提供了一种方法，其包括在衬底的动态随机存储区域（DRAM）中形成沟槽隔离结构，并且在沟槽结构上图案化蚀刻掩模以暴露沟槽结构的一部分。暴露的沟槽结构的一部分被去除以形成栅沟槽，其包括由衬底形成的第一角和由沟槽结构形成的第二角。去除蚀刻掩模，并且栅极沟槽的第一个角部被倒圆以形成圆角。随后在栅极沟槽，第一圆角和与栅极沟槽相邻的半导体衬底的侧壁上形成氧化物层。沟槽填充有栅极材料。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式