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1. 发明授权

US06574778B2 Block based design methodology 失效
公开(公告)号：US06574778B2
公开(公告)日：2003-06-03
申请号：US09754725
申请日：2001-01-04
申请人： Henry Chang , Larry Cooke , Merrill Hunt , Wuudiann Ke , Christopher K. Lennard , Grant Martin , Peter Paterson , Khoan Truong , Kumar Venkatramani
发明人： Henry Chang , Larry Cooke , Merrill Hunt , Wuudiann Ke , Christopher K. Lennard , Grant Martin , Peter Paterson , Khoan Truong , Kumar Venkatramani
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F17/5022 , G06F2217/66
摘要： A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.

2. 发明授权

US06269467B1 Block based design methodology 有权
标题翻译：基于块的设计方法
公开(公告)号：US06269467B1
公开(公告)日：2001-07-31
申请号：US09410356
申请日：1999-09-30
申请人： Henry Chang , Larry Cooke , Merrill Hunt , Wuudiann Ke , Christopher K. Lennard , Grant Martin , Peter Paterson , Khoan Truong , Kumar Venkatramani
发明人： Henry Chang , Larry Cooke , Merrill Hunt , Wuudiann Ke , Christopher K. Lennard , Grant Martin , Peter Paterson , Khoan Truong , Kumar Venkatramani
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F17/5022 , G06F2217/66
摘要： A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.
摘要翻译：一种用于设计电路系统的方法和装置，包括选择要用于设计电路系统的多个预先设计的电路块，收集反映设计者关于预先设计的电路块的体验的数据，设计者的经验可适应在接收时，基于设计者的经验数据和可接受的风险程度的方式接受或拒绝电路系统的设计，在接受时形成包含用于每个电路块的标准和修改的约束的块规格，形成用于在芯片的平面图上布置电路块的块规格，作为芯片上的系统，符合标准和修改的约束，并且基本上不改变所选择的电路块和处理方法。

3. 发明授权

US5774477A Method and apparatus for pseudorandom boundary-scan testing 失效
标题翻译：伪随机边界扫描测试的方法和装置
公开(公告)号：US5774477A
公开(公告)日：1998-06-30
申请号：US577454
申请日：1995-12-22
申请人： Wuudiann Ke
发明人： Wuudiann Ke
IPC分类号： G01R31/28 , G01R31/3183 , G01R31/3185 , G06F11/22
CPC分类号： G01R31/318385 , G01R31/318547
摘要： Pseudorandom Boundary-Scan testing of a interconnects within a system (10) is accomplished by first generating a pseudorandom pattern and then filtering the pattern before application to the system to modify values within each pattern that could cause a signal conflict. Each response generated by the system upon application to the system is also filtered to mask non-deterministic values with the response. The filtered response is compared to a set of signatures representing a fault-free condition to detect faults within the system.
摘要翻译：系统（10）内的互连的伪随机边界扫描测试通过首先产生伪随机模式然后在应用于系统之前对该模式进行过滤以修改每个模式内可能引起信号冲突的值来实现。系统在应用于系统时生成的每个响应也被过滤以屏蔽具有响应的非确定性值。将经过滤的响应与代表无故障状态的一组签名进行比较，以检测系统内的故障。

4. 发明授权

US06629293B2 Block based design methodology 有权
公开(公告)号：US06629293B2
公开(公告)日：2003-09-30
申请号：US09754466
申请日：2001-02-23
申请人： Henry Chang , Larry Cooke , Merrill Hunt , Wuudiann Ke , Christopher K. Lennard , Grant Martin , Peter Paterson , Khoan Truong , Kumar Venkatramani
发明人： Henry Chang , Larry Cooke , Merrill Hunt , Wuudiann Ke , Christopher K. Lennard , Grant Martin , Peter Paterson , Khoan Truong , Kumar Venkatramani
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F17/5022 , G06F2217/66
摘要： A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.

5. 发明授权

US06594800B2 Block based design methodology 有权
公开(公告)号：US06594800B2
公开(公告)日：2003-07-15
申请号：US09754559
申请日：2001-01-04
申请人： Henry Chang , Larry Cooke , Merrill Hunt , Wuudiann Ke , Christopher K. Lennard , Grant Martin , Peter Paterson , Khoan Truong , Kumar Venkatramani
发明人： Henry Chang , Larry Cooke , Merrill Hunt , Wuudiann Ke , Christopher K. Lennard , Grant Martin , Peter Paterson , Khoan Truong , Kumar Venkatramani
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F17/5022 , G06F2217/66
摘要： A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.

6. 发明授权

US6108807A Apparatus and method for hybrid pin control of boundary scan applications 失效
标题翻译：边界扫描应用的混合引脚控制的装置和方法
公开(公告)号：US6108807A
公开(公告)日：2000-08-22
申请号：US901250
申请日：1997-07-28
申请人： Wuudiann Ke
发明人： Wuudiann Ke
IPC分类号： G01R31/28
CPC分类号： G01R31/318572
摘要： In accordance with the present invention, an apparatus and method for implementing a new user-defined B-S instruction called PINCONTROL is disclosed. When PINCONTROL is in effect, an output pin can be configured to be either driving a constant 0, driving a 1, in the high-impedance (high-Z) state or in the control of system logic; and different pins of the same chips may assume different configurations depending on the content of the capture and update portion of the B-S register. This instruction provides an improved fault insertion capability. For example, if it is desired to inject a stuck-at-0 fault at pin p, pin p can be configured to drive a constant 0 while allowing other pins to function normally. A stuck-at-1 fault can also be injected by configuring pin p to drive a constant 0 while allowing other pins to function normally. An open fault can also be injected by configuring pin p into a high-impedance state. As will described, multiple faults of the same or different type may be injected, as can transient faults with different durations. This kind of fault insertion capability can be used to verify the fault-tolerant capability of a fault-tolerant system and for the verification of system diagnostics software.
摘要翻译：根据本发明，公开了一种用于实现称为PINCONTROL的新用户定义的B-S指令的装置和方法。当PINCONTROL有效时，可以将输出引脚配置为在高阻抗（高Z）状态或系统逻辑控制中驱动常数0，驱动1，并且根据B-S寄存器的捕获和更新部分的内容，相同芯片的不同引脚可以呈现不同的配置。该指令提供了改进的故障插入能力。例如，如果希望在引脚p注入卡在0故障，则可以将引脚p配置为驱动常数0，同时允许其他引脚正常工作。也可以通过配置引脚p来驱动常数0，同时允许其他引脚正常工作来注入卡住1故障。也可以通过将引脚p配置为高阻抗状态来注入开路故障。如上所述，可以注入相同或不同类型的多个故障，以及具有不同持续时间的瞬态故障。这种故障插入功能可用于验证容错系统的容错能力和验证系统诊断软件。

7. 发明授权

US06725432B2 Blocked based design methodology 有权
标题翻译：基于阻塞的设计方法
公开(公告)号：US06725432B2
公开(公告)日：2004-04-20
申请号：US09754724
申请日：2001-03-23
申请人： Henry Chang , Larry Cooke , Merrill Hunt , Wuudiann Ke , Christopher K. Lennard , Grant Martin , Peter Paterson , Khoan Truong , Kumar Venkatramani
发明人： Henry Chang , Larry Cooke , Merrill Hunt , Wuudiann Ke , Christopher K. Lennard , Grant Martin , Peter Paterson , Khoan Truong , Kumar Venkatramani
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F17/5022 , G06F2217/66
摘要： A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.
摘要翻译：一种用于设计电路系统的方法和装置，包括选择要用于设计电路系统的多个预先设计的电路块，收集反映设计者关于预先设计的电路块的体验的数据，设计者的经验可适应在接收时，基于设计者的经验数据和可接受的风险程度的方式接受或拒绝电路系统的设计，在接受时形成包含用于每个电路块的标准和修改的约束的块规格，形成用于在芯片的平面图上布置电路块的块规格，作为芯片上的系统，符合标准和修改的约束，并且基本上不改变所选择的电路块和处理方法。

8. 发明授权

US06701504B2 Block based design methodology 有权
标题翻译：基于块的设计方法
公开(公告)号：US06701504B2
公开(公告)日：2004-03-02
申请号：US09754653
申请日：2001-01-04
申请人： Henry Chang , Larry Cooke , Merrill Hunt , Wuudiann Ke , Christopher K. Lennard , Grant Martin , Peter Paterson , Khoan Truong , Kumar Venkatramani
发明人： Henry Chang , Larry Cooke , Merrill Hunt , Wuudiann Ke , Christopher K. Lennard , Grant Martin , Peter Paterson , Khoan Truong , Kumar Venkatramani
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F17/5022 , G06F2217/66
摘要： A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.
摘要翻译：一种用于设计电路系统的方法和装置，包括选择要用于设计电路系统的多个预先设计的电路块，收集反映设计者关于预先设计的电路块的体验的数据，设计者的经验可适应在接收时，基于设计者的经验数据和可接受的风险程度的方式接受或拒绝电路系统的设计，在接受时形成包含用于每个电路块的标准和修改的约束的块规格，形成用于在芯片的平面图上布置电路块的块规格，作为芯片上的系统，符合标准和修改的约束，并且基本上不改变所选择的电路块和处理方法。

9. 发明授权

US06698002B2 Blocked based design methodology 有权
公开(公告)号：US06698002B2
公开(公告)日：2004-02-24
申请号：US09754640
申请日：2001-03-23
申请人： Henry Chang , Larry Cooke , Merrill Hunt , Wuudiann Ke , Christopher K. Lennard , Grant Martin , Peter Paterson , Khoan Truong , Kumar Venkatramani
发明人： Henry Chang , Larry Cooke , Merrill Hunt , Wuudiann Ke , Christopher K. Lennard , Grant Martin , Peter Paterson , Khoan Truong , Kumar Venkatramani
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F17/5022 , G06F2217/66
摘要： A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.

10. 发明授权

US06694501B2 Block based design methodology 有权
公开(公告)号：US06694501B2
公开(公告)日：2004-02-17
申请号：US09754734
申请日：2001-01-04
申请人： Henry Chang , Larry Cooke , Merrill Hunt , Wuudiann Ke , Christopher K. Lennard , Grant Martin , Peter Paterson , Khoan Truong , Kumar Venkatramani
发明人： Henry Chang , Larry Cooke , Merrill Hunt , Wuudiann Ke , Christopher K. Lennard , Grant Martin , Peter Paterson , Khoan Truong , Kumar Venkatramani
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F17/5022 , G06F2217/66
摘要： A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.

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