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1. 发明授权

US4888735A ROM cell and array configuration 失效
标题翻译： ROM单元和阵列配置
公开(公告)号：US4888735A
公开(公告)日：1989-12-19
申请号：US187171
申请日：1988-04-28
申请人： Wung K. Lee , Stephen S. Chiao
发明人： Wung K. Lee , Stephen S. Chiao
IPC分类号： G11C16/04 , G11C16/10 , G11C17/12 , H01L27/115 , G11C11/40
CPC分类号： G11C17/12 , G11C16/0416 , G11C16/0425 , G11C16/10 , H01L27/115
摘要： An EPROM structure incorporating Vss isolation transistors having gates on wordlines shared by respective rows of conventional self-aligned EPROM cells, and having source and drain regions connected in series between EPROM cell source regions and the ground Vss terminal. An isolation transistor becomes conductive only when an EPROM cell sharing its wordline is selected. During programming, otherwise possible leakage current through unselected cells sharing the selected bitline is blocked by the Vss isolation transistor. Only one unselected adjacent cell, which shares a common source region with the selected cell, can leak. This leakage, if properly suppressed and compensated, has no disturbance on the unselected or selected cells during array programming. The EPROM cell drain punchthrough voltage and channel length can thus be reduced to obtain ROM and EPROM cells with low threshold voltages, low drain programming voltages, short programming times, low cell junction and bitline capacitances, and high read currents. EPROM-type products can be constructed with single low power supplies, on-chip high voltage pumping and high speed read and programming. Additional rows of shared isolation transistors can be formed by adding extra poly(2) lines in parallel to the wordlines betwen EPROM source diffusions to achieve fuller programming isolation. This cell and array isolation configuration can be extended to flash EEPROM type products. The cell and array configuration of the present invention can also be embodied in ROM type products by omitting the poly(1) floating gates underneath the poly(2) worlines in ROM cells.
摘要翻译：一种EPROM结构，其包含具有由常规自对准EPROM单元的各行共享的字线上的栅极的Vss隔离晶体管，并且具有串联连接在EPROM单元源区域和地Vss端子之间的源极和漏极区域。只有当选择共享其字线的EPROM单元时，隔离晶体管才导通。在编程期间，否则通过共享所选位线的未选择单元的泄漏电流可能被Vss隔离晶体管阻挡。只有一个与所选择的单元共享共用源区域的未选择的相邻单元可能泄漏。如果正确地抑制和补偿了这种泄漏，则在阵列编程期间对未选择的或选定的单元没有干扰。因此可以减小EPROM单元漏极穿通电压和沟道长度，以获得具有低阈值电压，低漏编程电压，短编程时间，低单元结和位线电容以及高读电流的ROM和EPROM单元。 EPROM型产品可以采用单个低电源，片上高压抽运和高速读写编程。可以通过在EPROM源扩散之间的字线并行添加额外的多（2）线来实现更多的编程隔离来形成额外的共享隔离晶体管行。该单元和阵列隔离配置可以扩展到闪存EEPROM类型的产品。本发明的电池和阵列结构也可以通过省略ROM单元中的多晶硅（2）工作线下方的多晶硅（1）浮栅来体现在ROM型产品中。

2. 发明授权

US4888734A EPROM/flash EEPROM cell and array configuration 失效
标题翻译： EPROM /闪存EEPROM单元和阵列配置
公开(公告)号：US4888734A
公开(公告)日：1989-12-19
申请号：US139885
申请日：1987-12-28
申请人： Wung K. Lee , Stephen S. Chiao
发明人： Wung K. Lee , Stephen S. Chiao
IPC分类号： G11C16/04 , G11C16/10 , G11C17/12 , H01L27/115
CPC分类号： G11C17/12 , G11C16/0416 , G11C16/0425 , G11C16/10 , H01L27/115
摘要： An EPROM structure incorporating Vss isolation transistors having gates on wordlines shared by respective rows of conventional self-aligned EPROM cells, and having source and drain regions connected in series between EPROM cell source regions and the ground Vss terminal. An isolation transistor becomes conductive only when an EPROM cell sharing its wordline is selected. During programming, otherwise possible leakage current through unselected cells sharing the selected bitline is blocked by the Vss isolation transistor. Only one unselected adjacent cell, which shares a common source region with the selected cell, can leak. This leakage, if properly suppressed and compensated, has no disturbance on unselected or selected cells during array programming. The EPROM cell drain punchthrough voltage and channel length can thus be reduced to obtain an EPROM cell with a low threshold voltage, low drain programming voltage, short programming time, low cell junction and bitline capacitance, and high read current. EPROM-type products can be constructed with single low power supplies, on-chip high voltage pumping and high speed read and programming. Additional rows of shared isolation transistors can be formed by adding extra poly2 lines in parallel to the wordlines between EPROM source diffusions to achieve fuller programming isolation. This cell and array isolation configuration can be extended to flash EEPROM type products.
摘要翻译：一种EPROM结构，其包含具有由常规自对准EPROM单元的各行共享的字线上的栅极的Vss隔离晶体管，并且具有串联连接在EPROM单元源区域和地Vss端子之间的源极和漏极区域。只有当选择共享其字线的EPROM单元时，隔离晶体管才导通。在编程期间，否则通过共享所选位线的未选择单元的泄漏电流可能被Vss隔离晶体管阻挡。只有一个与所选择的单元共享共用源区域的未选择的相邻单元可能泄漏。如果正确地抑制和补偿了这种泄漏，在阵列编程期间对未选择或选定的单元没有干扰。因此可以减小EPROM单元漏极穿通电压和沟道长度，以获得具有低阈值电压，低漏编程电压，短编程时间，低单元结和位线电容以及高读电流的EPROM单元。 EPROM型产品可以采用单个低电源，片上高压抽运和高速读写编程。额外的共享隔离晶体管行可以通过在EPROM源扩散之间添加额外的poly2线与字线并行来实现更完整的编程隔离来形成。该单元和阵列隔离配置可以扩展到闪存EEPROM类型的产品。

3. 发明授权

US4868617A Gate controllable lightly doped drain mosfet devices 失效
标题翻译：门可控轻掺杂漏极MOSFET器件
公开(公告)号：US4868617A
公开(公告)日：1989-09-19
申请号：US185719
申请日：1988-04-25
申请人： Stephen S. Chiao , Wung K. Lee
发明人： Stephen S. Chiao , Wung K. Lee
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/6659 , H01L29/6656 , H01L29/7836 , Y10S257/90
摘要： An LDD MOSFET structure in which gate sidewall spacers are formed of polycrystalline silicon and electrically shorted to the gate to extend gate control over the LDD region surface oxide and thereby reduce and control interface charge trapping without increasing substrate currents.
摘要翻译： LDD MOSFET结构，其中栅极侧壁间隔物由多晶硅形成并且电短路到栅极以扩展LDD区域表面氧化物上的栅极控制，从而减少和控制界面电荷捕获而不增加衬底电流。

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