专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09052604B2 Photolithography systems and associated alignment correction methods 有权
标题翻译：光刻系统和相关的对准校正方法
公开(公告)号：US09052604B2
公开(公告)日：2015-06-09
申请号：US12266202
申请日：2008-11-06
申请人： Woong Jae Chung
发明人： Woong Jae Chung
IPC分类号： G03F9/00
CPC分类号： G03F9/7003 , G03F9/7046 , G03F9/7092
摘要： Several embodiments of photolithography systems and associated methods of alignment correction are disclosed herein. In one embodiment, a method for correcting alignment errors in a photolithography system includes detecting a first alignment error at a first location of a first microelectronic substrate and a second alignment error at a second location of a second microelectronic substrate. The second location generally corresponds to the first location. The method also includes deriving a statistical dispersion between the first alignment error and the second alignment error and associating the first and second locations with an alignment procedure based on the derived statistical dispersion.
摘要翻译：本文公开了光刻系统和相关联的对准校正方法的几个实施例。在一个实施例中，用于校正光刻系统中的对准误差的方法包括检测第一微电子衬底的第一位置处的第一对准误差和在第二微电子衬底的第二位置处的第二对准误差。第二位置通常对应于第一位置。该方法还包括导出第一对准误差和第二对准误差之间的统计色散，并且基于导出的统计色散将第一和第二位置与对准过程相关联。

2. 发明授权

US08203695B2 Photolithography systems and associated methods of focus correction 有权
标题翻译：光刻系统和相关的焦点校正方法
公开(公告)号：US08203695B2
公开(公告)日：2012-06-19
申请号：US12264109
申请日：2008-11-03
申请人： Woong Jae Chung
发明人： Woong Jae Chung
IPC分类号： G03B27/52 , G03B27/42 , G03B27/32 , G03B27/68 , G03B27/58
CPC分类号： G03F7/70641
摘要： Several embodiments of photolithography systems and associated methods of focus correction are disclosed herein. In one embodiment, a method for characterizing focus errors in a photolithography system includes placing a microelectronic substrate onto a substrate support of the photolithography system. The microelectronic substrate is divided into a plurality of fields individually partitioned into a plurality of regions. The method also includes developing a raw focus error map that has a focus error corresponding to the individual regions of the plurality of fields and deriving at least one of an inter-field focus error map and an intra-field focus error map based on the raw focus error map. The inter-field focus error map has an inter-field focus error corresponding to the individual fields, and the intra-field focus error map has an intra-field focus error corresponding to the individual regions.
摘要翻译：本文公开了光刻系统和相关联的聚焦校正方法的几个实施例。在一个实施例中，用于表征光刻系统中的焦点误差的方法包括将微电子衬底放置在光刻系统的衬底支撑件上。微电子衬底被分成多个单独划分成多个区域的场。该方法还包括开发具有与多个场的各个区域相对应的聚焦误差的原始聚焦误差图，并且基于原始图像导出场间聚焦误差图和场内聚焦误差图中的至少一个焦点错误图。场间聚焦误差图具有对应于各个场的场间聚焦误差，并且场内聚焦误差图具有对应于各个区域的场内聚焦误差。

3. 发明授权

US08260449B2 Photolithography systems and associated methods of overlay error correction 有权
标题翻译：光刻系统和相关的覆盖误差校正方法
公开(公告)号：US08260449B2
公开(公告)日：2012-09-04
申请号：US12266276
申请日：2008-11-06
申请人： Woong Jae Chung
发明人： Woong Jae Chung
IPC分类号： G06F19/00 , G03B27/32
CPC分类号： G05B19/41875 , G03B27/52 , G03F7/70633 , G05B2219/42155 , G05B2219/45028 , G05B2219/45031
摘要： Several embodiments of photolithography systems and associated methods of overlay error correction are disclosed herein. In one embodiment, a method for correcting overlay errors in a photolithography system includes measuring a plurality of first overlay errors that individually correspond to a microelectronic substrate in a first batch of microelectronic substrates. The method also includes determining a relationship between the first overlay errors and a first sequence of the microelectronic substrates in the first batch. The method further includes correcting a second overlay error of individual microelectronic substrates in a second batch based on a second sequence of the microelectronic substrates in the second batch and the determined relationship.
摘要翻译：本文公开了光刻系统的几个实施例和相关联的覆盖误差校正方法。在一个实施例中，用于校正光刻系统中的重叠误差的方法包括测量在第一批微电子衬底中分别对应于微电子衬底的多个第一覆盖误差。该方法还包括确定第一重叠误差与第一批中的微电子衬底的第一序列之间的关系。该方法还包括基于第二批中的微电子衬底的第二序列和确定的关系来校正第二批中的各个微电子衬底的第二重叠误差。

4. 发明申请

US20100114522A1 PHOTOLITHOGRAPHY SYSTEMS AND ASSOCIATED ALIGNMENT CORRECTION METHODS 有权
标题翻译：光刻系统和相关对齐校正方法
公开(公告)号：US20100114522A1
公开(公告)日：2010-05-06
申请号：US12266202
申请日：2008-11-06
申请人： Woong Jae Chung
发明人： Woong Jae Chung
IPC分类号： G06F15/00 , G01B11/00 , G03B27/54
CPC分类号： G03F9/7003 , G03F9/7046 , G03F9/7092
摘要： Several embodiments of photolithography systems and associated methods of alignment correction are disclosed herein. In one embodiment, a method for correcting alignment errors in a photolithography system includes detecting a first alignment error at a first location of a first microelectronic substrate and a second alignment error at a second location of a second microelectronic substrate. The second location generally corresponds to the first location. The method also includes deriving a statistical dispersion between the first alignment error and the second alignment error and associating the first and second locations with an alignment procedure based on the derived statistical dispersion.
摘要翻译：本文公开了光刻系统和相关联的对准校正方法的几个实施例。在一个实施例中，用于校正光刻系统中的对准误差的方法包括检测第一微电子衬底的第一位置处的第一对准误差和在第二微电子衬底的第二位置处的第二对准误差。第二位置通常对应于第一位置。该方法还包括导出第一对准误差和第二对准误差之间的统计色散，并且基于导出的统计色散将第一和第二位置与对准过程相关联。

5. 发明申请

US20080067688A1 Power-via structure for integration in advanced logic/smart-power technologies 有权
标题翻译：电源通道结构，用于集成先进的逻辑/智能电源技术
公开(公告)号：US20080067688A1
公开(公告)日：2008-03-20
申请号：US11525107
申请日：2006-09-20
申请人： Achim Gratz , Jakob Kriz , Woong-Jae Chung
发明人： Achim Gratz , Jakob Kriz , Woong-Jae Chung
IPC分类号： H01L23/52 , H01L21/44
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A via structure is disclosed for use in a multi-layered semiconductor device, for forming electrical contacts between prescribed layers of the vertically aligned structures. The via structures include a plurality of adjacent frame shaped hole structures which extend between the prescribed layers of the device, and which are filled with metal to form frame shaped vias. The width of each of the sides of the frame is chosen to be equal to an integer multiple of half of the minimum pitch of the semiconductor processing, with the distance between adjacent frame shaped via structures being approximately equal to an integer multiple of half of the minimum pitch of the semiconductor processing.
摘要翻译：公开了一种用于多层半导体器件中的通孔结构，用于在垂直排列的结构的规定层之间形成电接触。通孔结构包括在装置的规定层之间延伸并且被金属填充以形成框形通孔的多个相邻的框状孔结构。框架的每个边的宽度被选择为等于半导体处理的最小间距的一半的整数倍，相邻的框架形通孔结构之间的距离近似等于半导体处理的一半的整数倍半导体处理的最小间距。

6. 发明授权

US09195149B2 Photolithography systems and associated methods of overlay error correction 有权
标题翻译：光刻系统和相关的覆盖误差校正方法
公开(公告)号：US09195149B2
公开(公告)日：2015-11-24
申请号：US13598467
申请日：2012-08-29
申请人： Woong Jae Chung
发明人： Woong Jae Chung
IPC分类号： G03F7/20 , G03B27/52
CPC分类号： G05B19/41875 , G03B27/52 , G03F7/70633 , G05B2219/42155 , G05B2219/45028 , G05B2219/45031
摘要： Several embodiments of photolithography systems and associated methods of overlay error correction are disclosed herein. In one embodiment, a method for correcting overlay errors in a photolithography system includes measuring a plurality of first overlay errors that individually correspond to a microelectronic substrate in a first batch of microelectronic substrates. The method also includes determining a relationship between the first overlay errors and a first sequence of the microelectronic substrates in the first batch. The method further includes correcting a second overlay error of individual microelectronic substrates in a second batch based on a second sequence of the microelectronic substrates in the second batch and the determined relationship.
摘要翻译：本文公开了光刻系统的几个实施例和相关联的覆盖误差校正方法。在一个实施例中，用于校正光刻系统中的重叠误差的方法包括测量在第一批微电子衬底中分别对应于微电子衬底的多个第一覆盖误差。该方法还包括确定第一重叠误差与第一批中的微电子衬底的第一序列之间的关系。该方法还包括基于第二批中的微电子衬底的第二序列和确定的关系来校正第二批中的各个微电子衬底的第二重叠误差。

7. 发明申请

US20120320349A1 PHOTOLITHOGRAPHY SYSTEMS AND ASSOCIATED METHODS OF OVERLAY ERROR CORRECTION 有权
标题翻译：相片校正系统及其相关方法
公开(公告)号：US20120320349A1
公开(公告)日：2012-12-20
申请号：US13598467
申请日：2012-08-29
申请人： Woong Jae Chung
发明人： Woong Jae Chung
IPC分类号： G03B27/32
CPC分类号： G05B19/41875 , G03B27/52 , G03F7/70633 , G05B2219/42155 , G05B2219/45028 , G05B2219/45031
摘要： Several embodiments of photolithography systems and associated methods of overlay error correction are disclosed herein. In one embodiment, a method for correcting overlay errors in a photolithography system includes measuring a plurality of first overlay errors that individually correspond to a microelectronic substrate in a first batch of microelectronic substrates. The method also includes determining a relationship between the first overlay errors and a first sequence of the microelectronic substrates in the first batch. The method further includes correcting a second overlay error of individual microelectronic substrates in a second batch based on a second sequence of the microelectronic substrates in the second batch and the determined relationship.
摘要翻译：本文公开了光刻系统的几个实施例和相关联的覆盖误差校正方法。在一个实施例中，用于校正光刻系统中的重叠误差的方法包括测量在第一批微电子衬底中分别对应于微电子衬底的多个第一覆盖误差。该方法还包括确定第一重叠误差与第一批中的微电子衬底的第一序列之间的关系。该方法还包括基于第二批中的微电子衬底的第二序列和确定的关系来校正第二批中的各个微电子衬底的第二重叠误差。

8. 发明授权

US08313877B2 Photolithography monitoring mark, photolithography mask comprising an exposure monitoring mark, and phase shift mask comprising an exposure monitoring mark 有权
标题翻译：光刻监视标记，包括曝光监视标记的光刻掩模和包括曝光监视标记的相移掩模
公开(公告)号：US08313877B2
公开(公告)日：2012-11-20
申请号：US12483706
申请日：2009-06-12
申请人： Woong Jae Chung
发明人： Woong Jae Chung
IPC分类号： G03F9/00 , G03F1/00 , H01L23/544
CPC分类号： G03F1/26 , G03F1/44
摘要： A photolithography monitoring mark on a substrate includes a plurality of sets of lines. Individual of the sets include a plurality of substantially parallel lines comprising different widths arrayed laterally outward in opposing lateral directions from an axial center of the set. The different widths decrease in each of the opposing lateral directions laterally outward from the axial center of the set. Other implementations are disclosed.
摘要翻译：基板上的光刻监视标记包括多组线。这些组的个体包括多个基本上平行的线，包括从组的轴向中心沿相对的横向方向横向向外排列的不同宽度。从组的轴向中心横向向外的每个相对的横向方向上的不同的宽度减小。公开了其他实现。

9. 发明申请

US20100110401A1 PHOTOLITHOGRAPHY SYSTEMS AND ASSOCIATED METHODS OF FOCUS CORRECTION 有权
标题翻译：光刻校正系统及其相关方法
公开(公告)号：US20100110401A1
公开(公告)日：2010-05-06
申请号：US12264109
申请日：2008-11-03
申请人： Woong Jae Chung
发明人： Woong Jae Chung
IPC分类号： G03B27/52 , G03B43/00
CPC分类号： G03F7/70641
摘要： Several embodiments of photolithography systems and associated methods of focus correction are disclosed herein. In one embodiment, a method for characterizing focus errors in a photolithography system includes placing a microelectronic substrate onto a substrate support of the photolithography system. The microelectronic substrate is divided into a plurality of fields individually partitioned into a plurality of regions. The method also includes developing a raw focus error map that has a focus error corresponding to the individual regions of the plurality of fields and deriving at least one of an inter-field focus error map and an intra-field focus error map based on the raw focus error map. The inter-field focus error map has an inter-field focus error corresponding to the individual fields, and the intra-field focus error map has an intra-field focus error corresponding to the individual regions.
摘要翻译：本文公开了光刻系统和相关联的聚焦校正方法的几个实施例。在一个实施例中，用于表征光刻系统中的焦点误差的方法包括将微电子衬底放置在光刻系统的衬底支撑件上。微电子衬底被分成多个单独划分成多个区域的场。该方法还包括开发具有与多个场的各个区域相对应的聚焦误差的原始聚焦误差图，并且基于原始图像导出场间聚焦误差图和场内聚焦误差图中的至少一个焦点错误图。场间聚焦误差图具有对应于各个场的场间聚焦误差，并且场内聚焦误差图具有对应于各个区域的场内聚焦误差。

10. 发明授权

US07557444B2 Power-via structure for integration in advanced logic/smart-power technologies 有权
标题翻译：电源通道结构，用于集成先进的逻辑/智能电源技术
公开(公告)号：US07557444B2
公开(公告)日：2009-07-07
申请号：US11525107
申请日：2006-09-20
申请人： Achim Gratz , Jakob Kriz , Woong-Jae Chung
发明人： Achim Gratz , Jakob Kriz , Woong-Jae Chung
IPC分类号： H01L23/48
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A via structure is disclosed for use in a multi-layered semiconductor device, for forming electrical contacts between prescribed layers of the vertically aligned structures. The via structures include a plurality of adjacent frame shaped hole structures which extend between the prescribed layers of the device, and which are filled with metal to form frame shaped vias. The width of each of the sides of the frame is chosen to be equal to an integer multiple of half of the minimum pitch of the semiconductor processing, with the distance between adjacent frame shaped via structures being approximately equal to an integer multiple of half of the minimum pitch of the semiconductor processing.
摘要翻译：公开了一种用于多层半导体器件中的通孔结构，用于在垂直排列的结构的规定层之间形成电接触。通孔结构包括在装置的规定层之间延伸并且被金属填充以形成框形通孔的多个相邻的框状孔结构。框架的每个边的宽度被选择为等于半导体处理的最小间距的一半的整数倍，相邻的框架形通孔结构之间的距离近似等于半导体处理的一半的整数倍半导体处理的最小间距。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式